View MB91220_4187752.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16806-1E
32-bit Microcontroller
CMOS
FR60Lite MB91220/S Series
MB91F223/F223S/MB91V220
OVERVIEW
MB91220/S series is a line of single-chip microcontrollers based on a 32-bit high-performance RISC CPU and integrating a variety of I/O resources for embedded control applications. The MB91220/S series is designed to be best suited for embedded applications which require high-speed and high-performance processing power in the CPU, such as DVD players, printers, TV sets, and the PDP control.The MB91220/S series is a line of CPUs in the FR60Lite implemented by FR* family. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2007 FUJITSU LIMITED All rights reserved
MB91220/S Series
FEATURES
* FR60Lite CPU * 32-bit RISC, load/store architecture, 5-stage pipeline * Maximum operating frequency : 32 MHz (Source oscillation is 4 MHz with x8 multiplier-PLL clock multiplier system) * 16-bit fixed-length instructions (basic instructions) * Instruction execution speed : 1 instruction per cycle * Instruction set optimized for embedded application : Memory-to-memory transfer, bit manipulation, barrel shift instructions etc. * Instructions supported by C language : Function entry/exit instructions, multiple-register load/store instructions. * Register interlock function : Easier assembler coding enabled * Built-in multiplier supported at the instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupt (PC/PS save) : 6 cycles (16 priority levels) * Harvard architecture allowing program access and data access to be executed simultaneously. * Instruction set compatible with FR family * Internal Peripheral Functions * Internal ROM size & ROM type Flash Memory : 512 Kbytes (MB91F223/S) * Internal RAM size : 16 Kbytes (MB91F223/S) / 64 Kbytes (MB91V220) * General-purpose ports : up to 120 ports (including 4 input-only ports) * 8/10-bit A/D converter (Sequential comparison type) 8/10-bit resolution : 24 channels Conversion time : 3 s (16/32 MHz) Set the PLL multiplier and the division ratio of peripheral circuit clocks so that the above conversion time is achieved. 32 MHz : Source oscillation (4 MHz) with x8 multiplier, divided by 1 16 MHz : Source oscillation with x8 multiplier, divided by 2 * D/A converter (R-2R type) 8-bit resolution : 2 channels * External interrupt : 8 channels * Bit search module (for REALOS) * LIN-UART (full duplex double buffer type) : 4 channels Synchronous/asynchronous clock operations selectable Sync-break detection Dedicated built-in baud-rate generator * I2C Bus interface* : 2 channels * Stepping motor controller (SMC) : 4 channels 10-bit PWM with 4 high-current outputs for each channel * 8/16-bit PPG timer : 16 channels * 16-bit reload timer : 3 channels * 16-bit free-run timer : 2 channels (ICU/OCU linkage) * 16-bit pulse width counter : 1 channel * Input capture : 4 channels (free-run timers ch.0 and ch.1). ch.0 linked to PWC * Output compare : 2 channels (free-run timer ch.0 ) * LCD controller : SEG0 to SEG31/COM0 to COM3 (shared with port) * 16-bit timebase/watch dog timer (Continued) 2
MB91220/S Series
(Continued) * Sound generator : 3 channels * Real-time clock * 32 kHz sub clock (not supported in devices with an S suffix in the part number) * C-CAN : 2 channels * Low power consumption modes : sleep mode, stop mode, watch mode * Package : LQFP-144 (FPT-144P-M08) * CMOS technology : 0.35 m * Power supply voltage : 5 V (Internal logic : 3.3 V, I/O : 5.0 V (step-down circuit used)) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
3
MB91220/S Series
PRODUCT LINEUP
The table below shows the product lineup of the MB91220/S series. Embedded peripheral functions which are not listed are common functions. MB91V220 MB91F223/S ROM/Flash size RAM size External interrupt DMA Controller 8 /10-bit A/D Converter D/A Converter LIN-UART I2C Stepping Motor Controller 8 /16-bit PPG Timer 16-bit Reload Timer 16-bit Free-Run Timer 16-bit Pulse Width Counter Input Capture Unit Output Compare Unit LCD Controller Sound Generator Real Time Clock 32 kHz Sub Clock External bus Others On Chip Debug Support Unit C-CAN Evaluation product DSU4 2 channels 32-message buffer Yes Addr 16 bits Data 16 bits Flash memory product External SRAM 64 Kbytes 8 channels 5 channels 24 channels 2 channels 4 channels 2 channels 4 channels 16 channels 3 channels 2 channels 1 channel 4 channels 2 channels 4 COM, 32 SEG 3 channels Yes Yes : MB91F223 No : MB91F223S 512 Kbytes 16 Kbytes
4
MB91220/S Series
PIN ASSIGNMENT
(TOP VIEW)
P20/SEG0/A00 PD7/COM3/PPG7H PD6/COM2/PPG5H PD5/COM1/PPG3H PD4/COM0/PPG1H PD3/IN3/V3 PD2/TIN2/INT2/V2 PD1/TIN1/IN1/V1 PD0/TIN0/IN0/PWC0/INT2/V0 P47/SYSCLK P46/ASX P57/OUT1/RDY P56/OUT0/WR1X P55/SCK5/WR0X P54/SOT5/RDX X0 X1 VSS VCC P53/SIN5/CK1/CS3X P52/SCK4/CS2X P51/SOT4/CS1X P50/SIN4/CK0/CS0X P45/SCK3 P44/SOT3 P43/SIN3/INT1 P42/SCK0 P41/SOT0 P40/SIN0/INT0 PG3/TOT2/PPG6H PG2/TOT1/PPG4H PG1/TOT0/PPG2H P73/TX1 P72/INT7/RX1 P71/TX0 P70/INT6/RX0
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
P21/SEG1/A01 P22/SEG2/A02 P23/SEG3/A03 P24/SEG4/A04 P25/SEG5/A05 P26/SEG6/A06 P27/SEG7/A07 P30/SEG8/A08 P31/SEG9/A09 P32/SEG10/A10 P33/SEG11/A11 P34/SEG12/A12 P35/SEG13/A13 P36/SEG14/A14 P37/SEG15/A15 X0A X1A VCC VSS VCC3C P10/SEG16/D08 P11/SEG17/D09 P12/SEG18/D10 P13/SEG19/D11 P14/SEG20/D12 P15/SEG21/D13 P16/SEG22/D14 P17/SEG23/D15 P00/SEG24/D00 P01/SEG25/D01 P02/SEG26/D02 P03/SEG27/D03 P04/SEG28/D04 P05/SEG29/D05 P06/SEG30/D06 P07/SEG31/ATGX/D07
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
INITX MD0 MD1 MD2 DVSS DVCC PE7/PPG15H/SCL1 PE6/PPG14H/SDA1 PE5/PPG13H/SCL0 PE4/PPG12H/SDA0 PE3/PWM2M2 PE2/PWM2P2 PE1/PWM1M2 PE0/PWM1P2 PA3/PWM2M3 PA2/PWM2P3 PA1/PWM1M3 PA0/PWM1P3 DVSS DVCC PF7/AN15 PF6/AN14 PF5/AN13 PF4/AN12 PF3/AN11 PF2/AN10 PF1/AN9 PF0/AN8 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
(FPT-144P-M08)
51
52
53
54
56 55
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AVSS/AVRL AVRH AVCC P80/AN16 P81/AN17 P82/AN18 P83/AN19 P84/AN20 P85/AN21/INT3 P86/AN22/INT4 P87/AN23/INT5 P90/DA0 P91/DA1 P92/SGA0 P93/SGO0 P94/SGA1 P95/SGO1 P96/SGA2 P97/SGO2 DVSS DVCC PC3/PWM2M0 PC2/PWM2P0 PC1/PWM1M0 PC0/PWM1P0 PB7/PWM2M1 PB6/PWM2P1 PB5/PWM1M1 PB4/PWM1P1 PB3/PPG11H PB2/PPG10H PB1/PPG9H PB0/PPG8H DVSS DVCC PG0/PPG0H
5
MB91220/S Series
PIN DESCRIPTIONS
Pin No. 129 128 16 17 108 105 106 107 Pin name X0 X1 X0A X1A INITX MD2 MD1 MD0 P00 to P06 29 to 35 SEG24 to SEG30 D00 to D06 P07 36 SEG31 ATGX D07 P10 to P17 21 to 28 SEG16 to SEG23 D08 to D15 P20 144 SEG0 A00 P21 to P27 1 to 7 SEG1 to SEG7 A01 to A07 P30 to P37 8 to 15 SEG8 to SEG15 A08 to A15 P40 SIN0 F F F G G G I/O circuit type* A A B B C D D D Main clock (oscillator) input. Main clock (oscillator) output. Sub clock (oscillator) input. Sub clock (oscillator) output. External reset input Mode pin 2. The setting on this pin determines the basic operation mode. Connect it to VCC or VSS. Mode pin 1. The setting on this pin determines the basic operation mode. Connect it to VCC or VSS. Mode pin 0. The setting on this pin determines the basic operation mode. Connect it to VCC or VSS. General-purpose I/O port SEG output from LCDC External data bus bit00 to bit06 General-purpose I/O port SEG output from LCDC External trigger input for A/D converter. External data bus bit07 General-purpose I/O port SEG outputs from LCDC External data bus bit08 to bit15 General-purpose I/O port SEG output from LCDC External address bus bit00 General-purpose I/O port SEG outputs from LCDC External address bus bit01 to bit07 General-purpose I/O port SEG outputs from LCDC External address bus bit08 to bit15 General-purpose I/O port: Valid when the data input specification is prohibited on UART0. M UART0 data input. Because this input is used as necessary while UART0 is used for input operation, the port output needs to be disabled except when it is used intentionally. External interrupt input. Because those inputs are used as necessary while the pertinent external interrupt is enabled, the port outputs need to be disabled except when they are used intentionally. (Continued) 6 Function
116
INT0
MB91220/S Series
Pin No.
Pin name P41
I/O circuit type*
Function General-purpose I/O port: Valid when the data output specification is prohibited on UART0. UART0 data output: Valid when the clock output specification is permitted on UART0 . General-purpose I/O port: Valid when the clock output specification is prohibited on UART0. UART0 clock input/output: Valid when the clock output specification is permitted on UART0. General-purpose I/O port: Valid when the data input specification is prohibited on LIN-UART1.
117 SOT0 P42 118 SCK0 P43 SIN3
I
I
119
M
UART1 data input. Because this input is used as necessary while UART1 is used for input operation, the port output needs to be disabled except when it is used intentionally. External interrupt input. Because those inputs are used as necessary while the pertinent external interrupt is enabled, the port outputs need to be disabled except when they are used intentionally. General-purpose I/O port: Valid when the data output specification on UART1 is prohibited. LIN-UART1 data output: Valid when the data output specification is permitted on LIN-UART1. General-purpose I/O port: Valid when the clock output specification is prohibited on LIN-UART1. LIN-UART1 clock input/output: Valid when the clock output specification is permitted on LIN-UART1. General-purpose I/O port Address strobe output: Valid when the address strobe output is permitted. General-purpose I/O port System clock output: Valid when the system clock output specification is permitted. A clock with the same frequency as that external bus operation frequency is output at this pin (Clock output stops at transition to the STOP state). General-purpose I/O port : Valid when the data input specification is prohibited on LIN-UART2.
INT1 P44 120 SOT3 P45 121 SCK3 134 P46 ASX P47 135 SYSCLK I I I I
P50 SIN4 CK0 CS0X
122
M
LIN-UART2 data input. Because this input is used as necessary while LIN-UART2 is used for input operation, the port output needs to be disabled except when it is used intentionally. External clock input for free-run timer 0 Chip select 0 output: Valid when the chip select 0 is permitted to output. (Continued)
7
MB91220/S Series
Pin No.
Pin name P51
I/O circuit type*
Function General-purpose I/O port: Valid when the data output specification is prohibited on LIN-UART2.
123
SOT4 CS1X P52
I
LIN-UART2 data output: Valid when the data output specification is permitted on LIN-UART2. Chip select 1 output: Valid when the output specification is permitted on chip select 1. General-purpose I/O port: Valid when clock output is prohibited on LIN-UART2.
124
SCK4 CS2X P53
I
LIN-UART2 clock input/output: Valid when the clock output specification is permitted on LIN-UART2. Chip select 2 output: Valid when the output specification is permitted on chip select 2. General-purpose I/O port: Valid when the data input specification is prohibited on LIN-UART3. LIN-UART3 data input. Because this input is used as necessary while LINUART3 is used for input operation, the port output needs to be disabled except when it is used intentionally. External clock input for free-run timer 1 Chip select 3 output: Valid when the output specification is permitted on chip select 3. General-purpose I/O port: Valid when data output specification is prohibited on LIN-UART3.
125
SIN5 CK1 CS3X P54
M
130
SOT5 RDX P55
I
LIN-UART3 data output: Valid when the data output specification is permitted on LIN-UART3. External bus read strobe output: Valid at the external bus mode. General-purpose I/O port: Valid when clock output is prohibited on LIN-UART3.
131
SCK5 WR0X P56
I
LIN-UART3 clock input/output: Valid when the clock output specification is permitted on LIN-UART3. External bus write strobe output: Valid when the WR0X output is permitted at the external bus mode. General-purpose I/O port Output compare output External bus write strobe output: Valid when the WR1X output is permitted at the external bus mode. General-purpose I/O port Output compare output External ready input: Valid when the external ready input specification is permitted. (Continued)
132
OUT0 WR1X P57
I
133
OUT1 RDY
J
8
MB91220/S Series
Pin No.
Pin name P60 to P67
I/O circuit type*
Function General-purpose I/O ports: Valid when analog input specification is prohibited. A/D converter analog inputs: Valid when the analog input is selected in the ADER register. General-purpose I/O port External interrupt input. Because this input is used as necessary while the pertinent external interrupt is enabled, the pot output need to be disabled except when it is used intentionally. RX0 input pin for CAN0 General-purpose I/O port TX0 input pin for CAN0 General-purpose I/O port External interrupt input. Because this input is used as necessary while the pertinent external interrupt is enabled, the pot output need to be disabled except when it is used intentionally. RX1 input pin for CAN1 General-purpose I/O port TX1 output pin for CAN1 General-purpose I/O port: Valid when analog input specification is prohibited. A/D converter analog inputs: Valid when the analog input is selected in the ADER register. General-purpose I/O port: Valid when analog input specification is prohibited.
73 to 80 AN0 to AN7 P70 109 INT6 RX0 110 P71 TX0 P72 111 INT7 RX1 112 P73 TX1 P80 to P84 69 to 65 AN16 to AN20 P85 AN21
E
I
I
I
I
E
64
E
A/D converter analog inputs: Valid when the analog input is selected in the ADER register. External interrupt input. Because this input is used as necessary while the pertinent external interrupt is enabled, the pot output need to be disabled except when it is used intentionally. General-purpose I/O port: Valid when analog input specification is prohibited.
INT3
P86 AN22
63
E
A/D converter analog inputs: Valid when the analog input is selected in the ADER register. External interrupt input. Because this input is used as necessary while the pertinent external interrupt is enabled, the pot output need to be disabled except when it is used intentionally. (Continued)
INT4
9
MB91220/S Series
Pin No.
Pin name P87 AN23
I/O circuit type*
Function General-purpose I/O port: Valid when analog input specification is prohibited.
62
E
A/D converter analog inputs: Valid when the analog input is selected in the ADER register. External interrupt input. Because this input is used as necessary while the pertinent external interrupt is enabled, the pot output need to be disabled except when it is used intentionally.
INT5 P90 DA0 P91 DA1 P92 SGA0 P93 SGO0 P94 SGA1 P95 SGO1 P96 SGA2 P97 SGO2 PA0 PWM1P3 PA1 PWM1M3 PA2 PWM2P3 PA3 PWM2M3 PB0 40 PPG8H PB1 41 PPG9H I I
61 60 59 58 57 56 55 54 91 92 93 94
L L I I I I I I H H H H
General-purpose I/O port D/A converter analog output General-purpose I/O port D/A converter analog output General-purpose I/O port Sound generator 0 output General-purpose I/O port Sound generator 0 output General-purpose I/O port Sound generator 1 output General-purpose I/O port Sound generator 1 output General-purpose I/O port Sound generator 2 output General-purpose I/O port Sound generator 2 output General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port PPG timer 8 output: Valid when the output specification is permitted on PPG timer 8. General-purpose I/O port PPG timer 9 output: Valid when the output specification is permitted on PPG timer 9. (Continued)
10
MB91220/S Series
Pin No.
Pin name PB2
I/O circuit type* General-purpose I/O port I
Function
42
PPG10H PB3
PPG timer 10 output: Valid when the output specification is permitted on PPG timer 10. General-purpose I/O port PPG timer 11 output: Valid when the output specification is permitted on PPG timer 11. General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port External event input pin for reload timer 0 Trigger input for input capture 0: Valid when input capture trigger input is permitted and an input port is specified. If this pin is selected for input capture input, it is used as necessary for input. Therefore the port output needs to be disabled except when it is used intentionally. PWC0 pulse width counter 0 input: Valid when the PWC0 pulse width counter 0 input is permitted. External interrupt input. Because those inputs are used as necessary while the pertinent external interrupt is enabled, the port outputs need to be disabled except when they are used intentionally. LCD driver power supply input pin (Continued)
43
PPG11H PB4 PWM1P1 PB5 PWM1M1 PB6 PWM2P1 PB7 PWM2M1 PC0 PWM1P0 PC1 PWM1M0 PC2 PWM2P0 PC3 PWM2M0 PD0 TIN0
I
44 45 46 47 48 49 50 51
H H H H H H H H
IN0 136 PWC0 K
INT2 V0
11
MB91220/S Series
Pin No.
Pin name PD1 TIN1
I/O circuit type* General-purpose I/O port
Function
External event input pin for reload timer 1 K Trigger input for input capture 1: Valid when input capture trigger input is permitted and an input port is specified. If this pin is selected for input capture input, it is used as necessary for input. Therefore the port output needs to be disabled except when it is used intentionally. LCD driver power supply input pin General-purpose I/O port External event input pin for reload timer 2 K Trigger input for input capture 2: Valid when input capture trigger input is permitted and an input port is specified. If this pin is selected for input capture input, it is used as necessary for input. Therefore the port output needs to be disabled except when it is used intentionally. LCD driver power supply input pin General-purpose I/O port Trigger input for input capture 3: Valid when input capture trigger input is permitted and an input port is specified. If this pin is selected for input capture input, it is used as necessary for input. Therefore the port output needs to be disabled except when it is used intentionally. LCD driver power supply input pin Power supply pin for the embedded ladder resistor. General-purpose I/O port F COM0 output from LCDC PPG timer 1 output: Valid when the output specification is permitted on PPG timer 1. General-purpose I/O port F COM1 output from LCDC PPG timer 3 output: Valid when the output specification is permitted on PPG timer 3. General-purpose I/O port F COM2 output from LCDC PPG timer 5 output: Valid when the output specification is permitted on PPG timer 5. General-purpose I/O port F COM3 output from LCDC PPG timer 7 output: Valid when the output specification is permitted on PPG timer 7. H General-purpose I/O port Stepping motor controller PWM output pin (Continued)
137
IN1 V1 PD2 TIN2
138
IN2 V2 PD3 IN3
139
K
V3 PD4 140 COM0 PPG1H PD5 141 COM1 PPG3H PD6 142 COM2 PPG5H PD7 143 COM3 PPG7H 95 PE0 PWM1P2
12
MB91220/S Series
(Continued) Pin No. Pin name PE1 PWM1M2 PE2 PWM2P2 PE3 PWM2M2 PE4 99 PPG12H SDA0 PE5 100 PPG13H SCL0 PE6 101 PPG14H SDA1 PE7 102 PPG15H SCL1 PF0 to PF7 81 to 88 AN8 to AN15 PG0 37 PPG0H PG1 113 TOT0 PPG2H PG2 114 TOT1 PPG4H PG3 115 TOT2 PPG6H I I I I E N N N N I/O circuit type* H H H General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port Stepping motor controller PWM output pin General-purpose I/O port PPG timer 12 output: Valid when the output specification is permitted on PPG timer 12. I2C0 serial data input/output pin General-purpose I/O port PPG timer 13 output: Valid when the output specification is permitted on PPG timer 13. I2C0 serial clock input/output pin General-purpose I/O port PPG timer 14 output: Valid when the output specification is permitted on PPG timer 14. I2C1 serial data input/output pin General-purpose I/O port PPG timer 15 output: Valid when the output specification is permitted on PPG timer 15. I2C1 serial clock input/output pin General-purpose I/O ports: Valid when analog input is prohibited. A/D converter analog inputs: Valid when the analog input is selected in the ADER register. General-purpose I/O port. PPG timer 0 output: Valid when the output specification is permitted on PPG timer 0. General-purpose I/O port External timer output for reload timer 0 PPG timer 2 output: Valid when the output specification is permitted on PPG timer 2. General-purpose I/O port External timer output for reload timer 1 PPG timer 4 output: Valid when the output specification is permitted on PPG timer 4. General-purpose I/O port External timer output for reload timer 2 PPG timer 6 output: Valid when the output specification is permitted on PPG timer 6. 13 Function
96 97 98
* : For information about the I/O circuit type, refer to " I/O CIRCUIT TYPE".
MB91220/S Series
[Power supply and GND pins] Pin No. Pin name 19, 127 18, 126 70 71 72 20 38, 52, 89, 103 39, 53, 90, 104 VSS VCC AVCC AVRH VCC3C DVCC DVSS
Function GND pins. The potentials of these pins must be the same. Power supply pins. The potentials of these pins must be the same. Analog power supply pin for A/D converter Analog reference power supply pin for A/D converter Capacitor coupling pin for internal regulator Power supply pins for stepping motor controller GND pins for stepping motor controller
AVSS/AVRL Analog GND or analog reference power supply pin for A/D converter
14
MB91220/S Series
I/O CIRCUIT TYPE
Group
X1
Circuit Type
Remarks For high speed (source oscillation of main clock) * Oscillation circuit * Feedback resistance X0 : approx. 1 M
Clock input
A
X0
Standby control
X1A
Clock input
For low speed (source oscillation of sub clock) * Oscillation circuit * Feedback resistance X0A : approx. 7 M
B
X0A
Standby control * Hysteresis (CMOS level) input * Pull-up resistor supported Pull-up resistor value = approx. 50 k * No standby control
P-ch R
P-ch
N-ch
C
R
CMOS hysteresis input (CMOS level) (Continued)
15
MB91220/S Series
Group
Circuit Type
Remarks * Flash memory product Hysteresis input High-voltage control for Flash test supported
N-ch N-ch
D
N-ch N-ch N-ch R
Control
Mode input Diffused resistor * CMOS output (4 mA) * Hysteresis (Automotive level) input (Standby control supported) * Analog input (Analog input is valid when the corresponding ADER bit is set to 1.)
P-ch
Digital output
N-ch
E
Digital output
R
Hysteresis input (Automotive level) Standby control Analog input
P-ch
Digital output
N-ch
Digital output F
R R
* CMOS output (4 mA) * LCDC output * Hysteresis (Automotive level) input (Standby control provided)
LCDC output Hysteresis input (Automotive level) Standby control (Continued)
16
MB91220/S Series
Group
P-ch
Circuit Type
Remarks * CMOS output (4 mA) * LCDC output * Hysteresis (Automotive level) input (Standby control supported) * Hysteresis (TTL level) input (Standby control supported)
Digital output
N-ch
Digital output G
R R R
LCDC output Hysteresis input (Automotive level) Hysteresis input (TTL level) Standby control * CMOS output High current output for PWM (30 mA) * Hysteresis (Automotive level) input (Standby control supported)
P-ch
Digital output
N-ch
H
R
Digital output
Hysteresis input (Automotive level) Standby control * CMOS output (4 mA) * Hysteresis (Automotive level) input (Standby control supported)
P-ch
Digital output
N-ch
I
Digital output
R
Hysteresis input (Automotive level) Standby control (Continued)
17
MB91220/S Series
Group
P-ch N-ch
Circuit Type
Remarks * CMOS output (4 mA) * Hysteresis (Automotive level) input (Standby control supported) * Hysteresis (TTL level) input (Standby control supported)
J
R R
Hysteresis input (Automotive level) Hysteresis input (TTL level) Standby control
P-ch
Hysteresis (Automotive level) input (Standby control supported)
N-ch
K
R
Hysteresis input (Automotive level) Standby control (Continued)
18
MB91220/S Series
(Continued) Group
P-ch N-ch
Circuit Type
Digital output Digital output
Remarks * CMOS output (4 mA) * D/A converter output * Hysteresis (automotive level) input (Standby control supported)
L
R R
Analog output Hysteresis input (Automotive level) STANDBY CONTROL
P-ch N-ch
Digital output Digital output
* CMOS output (4 mA) * Hysteresis (automotive level) input (standby control supported) * Hysteresis (CMOS level) input (Standby control supported)
M
R R
Hysteresis input (Automotive Level) Hysteresis input (CMOS level) STANDBY CONTROL Digital output (When I2C is used, P-ch is intercepted.) Digital output
P-ch N-ch
* CMOS output (3 mA) * Hysteresis (automotive level) input (Standby control supported) * Hysteresis (CMOS level) input (Standby control supported)
N
R R
Hysteresis input (Automotive Level) Hysteresis input (CMOS level) STANDBY CONTROL
19
MB91220/S Series
HANDLING DEVICES
* Preventing Latch-up Latch-up may occur in a CMOS IC, if a voltage greater than VCC or less than VSS is applied to input and output pin, or if an above-rating voltage is applied between VCC and VSS pins. When latch-up occurs, it may significantly increase the power supply current, and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. * Treatment of Unused Input Pins Do not leave unused input pins open, as this may cause a malfunction. Handle by performing a pull-up or pulldown with a resistance of 2 k or more. An unused I/O pin should be set to the output status and left open. When set to the input status, it should be handled in the same way as an input pin. * Power supply pins If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the pins to the external power supply and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source to the VCC and VSS pins of this device via a low impedance. Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device. This device incorporates a regulator. When using the device with 5 V power supply, apply that power supply to the VCC pin and always connect the VCC3C pin to a capacitor with 1 F or more for the purpose of regulator. * Example of power supply connection
5V 5V 5V
VCC DVCC AVCC AVRH
AVSS VSS DVSS
VCC3C 1 F
GND
20
MB91220/S Series
* Crystal oscillator circuit Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the PC board such that X0/X1 pins, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to the ground are placed as near one another as possible. When routing the X0 and X1 signals, they should be shielded for use on the board. Caution must be taken especially when using a pin next to the X0. It is strongly recommended that the PC board artwork be designed such that the X0, X1, X0A and X1A pins are surrounded by ground plane because stable operation can be expected with such a layout. In addition, the X0A/X1A pins must be surrounded by ground plane even if the sub clock is disabled. When using MB91F223S, connect the X0A pin to GND and leave the X1A pin open. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. * Mode pins (MD0 to MD2) These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS pin is as short as possible and the connection impedance is now. * Operation at start-up Always use the INITX pin to perform a setting initialization reset (INIT) after power-on. Immediately after poweron, hold the low level input to the INITX pin for the stabilization wait time required for the oscillator circuit, to take the oscillation stabilization wait time for the oscillator circuit. For INIT via the INITX pin, the oscillation stabilization wait time setting is initialized to the minimum value. * Source oscillation input upon power-on When power-on, always input the clock for the duration of the oscillation stabilization delay time. * Treatment of power supply pins on A/D converter Connect to ensure "AVCC = AVRH = VCC and AVSS = VSS" even if the A/D converter is not in use. * Power-on sequence for power supply analog input of A/D converter Always supply power to the A/D converter (AVCC and AVRH) and apply analog input (AN0 to AN 23) after turning on the digital power supply (VCC). Also, turn off the power supply for the A/D converter and analog input before turning off the digital power supply (VCC). AVR should not exceed AVCC when turning on and off. Even when using a pin shared with analog input as an input port, ensure that the input voltage does not exceed AVCC. * Handling power supply for high-current output buffer pin (DVCC, DVSS) Always apply power to high-current output buffer pins (DVCC) after turning on the digital power supply (VCC). In addition, turn off the power supply for the high-current output buffer pins before turning off the digital power supply (VCC). Apply the same power as for high-current output buffer pins even when using such pins as general-purpose ports (There is no problem in turning on or off the power supply for the high-current output buffer pins and the digital power supply at the same time). Always use the GND pin (DVSS) for the high-current output buffer pin at the same potential as the digital GND pin (VSS).
21
MB91220/S Series
* Switching from main clock mode to sub clock mode or stop mode Always stop the main clock after switching the main clock mode to the sub clock mode or stop mode. Also secure the oscillation stabilization wait time when returning from the sub clock mode or stop mode to the main clock mode. * Flash write Note that Flash write is not possible in the sub mode.
22
MB91220/S Series
BLOCK DIAGRAM
FR 60Lite CPU Core
32 32 5 channels DMAC DSU*2
Bit search
32
Flash 512 Kbytes
RAM 64 Kbytes/16 Kbytes
Bus converter
X0, X1 X0A, X1A*1 MD0 to MD2 INITX
Clock control Interrupt controller
16 32 adapter
2 channels C-CAN
RX0, RX1 TX0, TX1
PORT
16
PORT I/F 3 channels Reload timer 1 channel PWC timer
INT0 to INT7
8 channels External interrupt
TIN0 to TIN2 TOT0 to TOT2 PWC0
16 channels PPG timer
4 channels Input capture
ICU2 ICU3 ICU0 ICU1 OCU0 OCU1 FRT0 FRT1
PPG0H to PPG15H
IN0 to IN3
Real time clock CPU detect reset PWM1P0,PWM1P2 PWM1M0,PWM2P2 PWM2P0,PWM2M2 PWM2M0,PWM1M2 PWM1P1, PWM1P3 PWM1M1, PWM1M3 PWM2P1, PWM2P3 PWM2M1, PWM2M3
OUT0, OUT1
2 channels Output compare 2 channels Free-run timer
CK0, CK1 SGA0 to SGA2 SGO0 to SGO2 ATGX AVCC/AVSS AVRH AN0 to AN23 SIN0,SIN3 to SIN5 SOT0,SOT3 to SOT5 SCK0,SCK3 to SCK5
3 channels Sound Generator 24 channels A/D converter 4 channels LIN-UART
4 channels Stepper motor controller
32SEG x 4COM LCD controller 2 channels I2C 2 channels D/A converter
COM0 to COM3 SEG0 to SEG31 SDA0/SDA1 SCL0/SCL1 DA0/DA1
*1 : The devices with an S suffix in the part number does not support the sub-block. *2 : DSU is built into the MB91V220 only.
23
MB91220/S Series
MEMORY SPACE
* Memory space The FR family has 4 Gbytes logical address space (232 addresses) linearly accessible to the CPU space. * Direct addressing area The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during on instruction. The direct area varies depending on the size of data to be accessed as follows. Byte data access : 000H to 0FFH Halfword data access : 000H to 1FFH Word data access : 000H to 3FFH
24
MB91220/S Series
MEMORY MAP
MB91V220 Single chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 0000H 0002 01B4H 0003 0000H 0004 0000H 0005 0000H 0008 0000H I/O I/O I/O I/O
Internal ROM
External ROM
external bus mode
external bus mode
Direct
addressing area
Refer to " I/O MAP".
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
Access prohibited
Internal RAM 64 KB
Access prohibited
Internal RAM 64 KB
Access prohibited
Internal RAM 64 KB
Access prohibited Access prohibited Access prohibited
Emulation SRAM area
0010 0000H
Emulation SRAM area
External area
Access prohibited
FFFF FFFFH
External area
25
MB91220/S Series
MB91F223/S Single chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 0000H 0002 01B4H 0003 C000H 0004 0000H 0005 0000H 0008 0000H I/O I/O I/O I/O
Internal ROM
External ROM
external bus mode
external bus mode
Direct
addressing area
Refer to " I/O MAP".
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
Access prohibited
Internal RAM 16 KB
Access prohibited
Internal RAM 16 KB
Access prohibited
Internal RAM 16 KB
Access prohibited Access prohibited Flash memory area 512 Kbytes Access prohibited
FFFF FFFFH
Access prohibited Flash memory area 512 Kbytes External area
External area
0010 0000H
Note : Each mode is set depending on the mode vector fetch after INITX is negated. For mode settings, refer to " MODE SETTINGS".
26
MB91220/S Series
MODE SETTINGS
The FR family, sets the operation mode using mode pins (MD2 to MD0) and mode data. * Mode pins The mode pins (MD2 to MD0) specify how the mode vector fetch and reset vector fetch is performed. Other settings than these in the table are prohibited. Mode pin Mode name MD2 MD1 MD0 0 * Mode data Data written to the internal mode register (MODR) by mode vector fetch is called mode data. After an operating mode has been set in the mode register the device operates in that operating mode. The mode data is set by all reset sources. User programs cannot set data to the mode register. Details of mode data
bit31 0 bit30 0 bit29 0 bit28 0 bit27 0 bit26 ROMA bit25 WTH1 bit24 WTH2
Reset vector access area Internal
0
0
Internal ROM mode vector
Operating mode setting bits
Bit 31 to bit 27 are reserved. Always set the value to "00000B". Otherwise, the operation is not guaranteed. [bit26] ROMA (Internal ROM enabling bit) This bit specifies whether to enable internal ROM area. ROMA Function 0 1 External ROM mode Internal ROM mode Remarks
Internal F-bus RAM is enabled, and the internal ROM area (80000H to 100000H) becomes an external area.
Internal ROM area is enabled.
[bit25, bit24] WTH1, WTH0 (bus width setting bits) Specify the bus width for the external bus mode. In the external bus mode, this value is set to DBW1 and DBW0 bits in ACR0 (CS0 area). WTH1 WTH0 Function 0 0 1 1 0 1 0 1 8-bit bus width 16-bit bus width Single chip mode
27
MB91220/S Series
Note : Mode data set in the mode vector must be placed as byte data at 000FFFF8H. Place the data in the most significant byte from bit 31 to bit 24 as the FR family uses the big endian system for byte endian.
bit
31 XXXXXXXX
24 23 XXXXXXXX
16 15 XXXXXXXX
87 Mode Data
0
Incorrect
000FFFF8H
Correct
000FFFF8H 000FFFFCH
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
Reset vector
28
MB91220/S Series
I/O MAP
The following table shows the correspondence between the memory space area and each register of the peripheral resource. [How to read the map] Address
000000H
Register +0
PDR0 [R/W] B XXXXXXXX
+1
PDR1 [R/W] B XXXXXXXX
+2
PDR2 [R/W] B XXXXXXXX
+3
PDR3 [R/W] B XXXXXXXX
Block
T-unit Port data register
Read/Write attribute, Access unit (B : byte, H : halfword, W : word) Initial value after reset Register name (First-column register at address 4n; second-column register at 4n + 1, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : " 1 " : Initial value "1" " 0 " : Initial value "0" " X " : Initial value "undefined" "-" : No physical register present at this location Access by any undescribed data access attribute is prohibited.
29
MB91220/S Series
Address 00000000H 00000004H 00000008H 0000000CH 00000010H 00000014H to 0000003CH 00000040H
Register +0 PDR0[R/W] B,H XXXXXXXX PDR4[R/W] B,H XXXXXXXX PDR8[R/W] B,H XXXXXXXX PDRC[R/W] B,H ----XXXX PDRG[R/W] B,H ----XXXX +1 PDR1[R/W] B,H XXXXXXXX PDR5[R/W] B,H XXXXXXXX PDR9[R/W] B,H XXXXXXXX PDRD[R/W] B,H 0000XXXX +2 PDR2[R/W] B,H XXXXXXXX PDR6[R/W] B,H XXXXXXXX PDRA[R/W] B,H ----XXXX PDRE[R/W] B,H XXXXXXXX +3 PDR3[R/W] B,H XXXXXXXX PDR7[R/W] B,H ----XXXX PDRB[R/W] B,H XXXXXXXX PDRF[R/W] B,H XXXXXXXX -
Block
Port Data Register
EIRR0 [R/W] B,H,W XXXXXXXX DICR [R/W] B,H,W -------0 ENIR0 [R/W] B,H,W 00000000 HRCL[R/W] B 0--11111
Reserved
ELVR0 [R/W] B,H,W 00000000 00000000 TMR0[R] H,W XXXXXXXX XXXXXXXX TMCSR0[R/W] B,H,W ----0000 00000000 TMR1[R] H,W XXXXXXXX XXXXXXXX TMCSR1[R/W] B,H,W ----0000 00000000 TMR2[R] H,W XXXXXXXX XXXXXXXX TMCSR2[R/W] B,H,W ----0000 00000000 -
External Interrupt Delayed Interrupt Reload Timer 0
00000044H 00000048H 0000004CH 00000050H 00000054H 00000058H 0000005CH 00000060H to 00000064H 00000068H 0000006CH to 0000007CH
TMRLR0[W] H,W XXXXXXXX XXXXXXXX Reserved
TMRLR1[W] H,W XXXXXXXX XXXXXXXX TMRLR2[W] H,W XXXXXXXX XXXXXXXX -
Reload Timer 1
Reload Timer 2
Reserved DADR1[R/W] B, H, W XXXXXXXX DADR0[R/W] B, H, W XXXXXXXX
DACR1[R/W] B, H, W -------0
DACR0[R/W] B, H, W -------0 -
DAC
Reserved (Continued)
30
MB91220/S Series
Address
Register +0 SGAR0[R/W] B,H,W 00000000 SGAR1[R/W] B,H,W 00000000 SGAR2[R/W] B,H,W 00000000 LCDCMR[R/W] B,H,W ----0000 VRAM0 [R/W] B,H,W XXXXXXXX VRAM4 [R/W] B,H,W XXXXXXXX VRAM8 [R/W] B,H,W XXXXXXXX VRAM12[R/W] B,H,W XXXXXXXX +1 SGDBL0[R/W] B,H,W -------0 SGFR0[R/W] B,H,W XXXXXXXX SGDBL1[R/W] B,H,W -------0 SGFR1[R/W] B,H,W XXXXXXXX SGDBL2[R/W] B,H,W -------0 SGFR2[R/W] B,H,W XXXXXXXX VRAM1[R/W] B,H,W XXXXXXXX VRAM5 [R/W] B,H,W XXXXXXXX VRAM9 [R/W] B,H,W XXXXXXXX VRAM13[R/W] B,H,W XXXXXXXX SCR3 [R/W] B,H,W SMR3 [R/W] B,H,W SSR3 [R/W] B,H,W RDR3 [R/W] B,H,W 00000000 00000000 00001000 00000000 ESCR3[R/W] B,H,W 00000X00 ECCR3[R/ W] B,H,W 000000XX BGR13[R/W] B,H,W XXXXXXXX BGR03[R/W] B,H,W XXXXXXXX +2 +3
Block
00000080H
SGCR0[R/W] B,H,W 0-----00 000--000 SGTR0[R/W] B,H,W XXXXXXXX SGDR0[R/W] B,H,W XXXXXXXX
Sound Generator 0
00000084H
00000088H
SGCR1[R/W] B,H,W 0-----00 000--000 SGTR1[R/W] B,H,W XXXXXXXX SGDR1[R/W] B,H,W XXXXXXXX
Sound Generator 1
0000008CH
00000090H
SGCR2[R/W, R] B,H,W 0------00 000--000 SGTR2[R/W] B,H,W XXXXXXXX SGDR2[R/W] B,H,W XXXXXXXX
Sound Generator 2
00000094H
00000098H
LCR0 [R/W] B,H,W LCR1 [R/W] B,H,W 00010000 00000000 VRAM2 [R/W] B,H,W XXXXXXXX VRAM6 [R/W] B,H,W XXXXXXXX VRAM10[R/W] B,H,W XXXXXXXX VRAM14[R/W] B,H,W XXXXXXXX VRAM3 [R/W] B,H,W XXXXXXXX VRAM7 [R/W] B,H,W XXXXXXXX VRAM11[R/W] B,H,W XXXXXXXX VRAM15[R/W] B,H,W XXXXXXXX Reserved LCD Controller Driver
0000009CH
000000A0H
000000A4H
000000A8H 000000ACH 000000B0H 000000B4H 000000B8H 000000BCH
LIN-UART1
SCR4 [R/W] B,H,W SMR4 [R/W] B,H,W SSR4 [R/W] B,H,W RDR4 [R/W] B,H,W 00000000 00000000 00001000 00000000 ESCR4[R/W] B,H,W 00000X00 ECCR4[R/W] B,H,W 000000XX BGR14[R/W] B,H,W XXXXXXXX BGR04[R/W] B,H,W XXXXXXXX LIN-UART2
(Continued) 31
MB91220/S Series
Address 000000C0H
Register +0 +1 +2 +3 SCR5 [R/W] B,H,W SMR5 [R/W] B,H,W SSR5 [R/W] B,H,W RDR5 [R/W] B,H,W 00000000 00000000 00001000 00000000 ESCR5[R/W] B,H,W 00000X00 ECCR5[R/W] B,H,W 000000XX BGR15[R/W] B,H,W XXXXXXXX SSR0 [R/W, R] B,H,W 00001000 BGR10[R/W] B,H,W XXXXXXXX TCDT0 [R/W] H,W 00000000 00000000 TCDT1 [R/W] H,W 00000000 00000000 TCCS0 [R/W] B,H,W 00000000 TCCS1 [R/W] B,H,W 00000000 BGR05 [R/W] B,H,W XXXXXXXX RDR0 [R/W] B,H,W 00000000 BGR00[R/W] B,H,W XXXXXXXX
Block
LIN-UART3
000000C4H
000000C8H
SCR0 [R/W] B,H,W SMR0 [R/W] B,H,W 00000000 00000000 ESCR0[R/W] B,H,W 00000X00 ECCR0[R/W] B,H,W 000000XX
LIN-UART0
000000CCH 000000D0H 000000D4H
Reserved 16-bit Free-Run Timer 0 16-bit Free-Run Timer 1 Reserved IPCP0 [R] H,W XXXXXXXX XXXXXXXX ICS01 [R/W] B,H,W 00000000
000000D8H 000000DCH to 000000E0H 000000E4H 000000E8H 000000ECH 000000F0H 000000F4H to 00000104H 00000108H 0000010CH 00000110H 00000114H to 0000012CH
-
IPCP1 [R] H,W XXXXXXXX XXXXXXXX -
16-bit ICU 0, 1
IPCP3 [R] H,W XXXXXXXX XXXXXXXX -
IPCP2 [R] H,W XXXXXXXX XXXXXXXX ICS23 [R/W] B,H,W 00000000
16-bit ICU 2, 3
OCCP1 [R/W] H,W XXXXXXXX XXXXXXXX OCCP0 [R/W] H,W XXXXXXXX XXXXXXXX -
Reserved
16-bit OCU 0, 1
OCS01 [R/W] B,H,W 11101100 00001100 Reserved (Continued)
32
MB91220/S Series
Address 00000130H 00000134H 00000138H 0000013CH to 00000140H 00000144H 00000148H 0000014CH 00000150H
Register +0 +1 +2 +3 PWCSR0[R/W] B,H,W 0000000X 00000000 PDIVR0[R/W] B,H,W -----000 WTDBL [R/W] B -------0 WTCR [R/W] B,H 00000000 000-00-0 PWCR0[R] H,W 00000000 00000000 -
Block
PWC
Reserved
WTHR [R/W] B,H ---XXXXX
WTBR [R/W] B ---XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] B,H --XXXXXX WTSR [R/W] B --XXXXXX -
Real Time Clock
ADERH[R/W] B,H,W 11111111 11111111 ADCS1[R/W] B,H,W 00000000 ADCT1[R/W] B,H,W 00010000 ADCS0[R/W] B,H,W 00000000 ADCT0[R/W] B,H,W 00101100
ADERL[R/W] B,H,W 11111111 11111111 ADCR1[R] B,H,W ------XX ADSCH[R/W] B,H,W ---00000 ADCR0[R] B,H,W XXXXXXXX ADECH[R/W] B,H,W ---00000 Clock Calibrator
00000154H
ADC
00000158H
0000015CH 00000160H 00000164H
CUCR[R/W] B,H,W -------- ---0--00 CUTR1[R] B,H,W -------- 00000000 PWC20[R/W] H,W ------XX XXXXXXXX PWC0[R/W] B -0000--0 PWC21[R/W] H,W ------XX XXXXXXXX PWC1[R/W] B -0000--0 PWC22[R/W] H,W ------XX XXXXXXXX PWC2[R/W] B -0000--0
CUTD[R/W] B,H,W 10000000 00000000 CUTR2[R] B,H,W 00000000 00000000 PWC10[R/W] H,W ------XX XXXXXXXX PWS20[R/W] B,H,W -0000000 PWS10[R/W] B,H,W --000000
SMC0
00000168H
0000016CH
PWC11[R/W] H,W ------XX XXXXXXXX PWS21[R/W] B,H,W -0000000 PWS11[R/W] B,H,W --000000 SMC1
00000170H
00000174H
PWC12[R/W] H,W ------XX XXXXXXXX PWS22[R/W] B,H,W -0000000 PWS12[R/W] B,H,W --000000 SMC2
00000178H
(Continued) 33
MB91220/S Series
Address 0000017CH
Register +0 +1 +2 +3 PWC23[R/W] H,W ------XX XXXXXXXX PWC3[R/W] B -0000--0 PWC13[R/W] H,W ------XX XXXXXXXX PWS23[R/W] B,H,W -0000000 CANPRE[R/W] B,H,W 00000000 PWS13[R/W] B,H,W --000000
Block
SMC3
00000180H 00000184H to 000001A4H 000001A8H 000001ACH 000001B0H
Reserved
Reserved -
-
-
CAN Prescaler Reserved
-
TRG0[R/W] B,H,W 00000000
-
REVC0[R/W] B,H,W 00000000
000001B4H 000001B8H
PRLH0[R/W]B,H,W PRLL0[R/W]B,H,W PRLH1[R/W]B,H,W PRLL1[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PRLH2[R/W]B,H,W PRLL2[R/W]B,H,W PRLH3[R/W]B,H,W PRLL3[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PPGC0[R/W] B,H,W 0000000X PPGC1[R/W] B,H,W 0000000X PPGC2[R/W] B,H,W 0000000X PPGC3[R/W] B,H,W 0000000X
000001BCH
PPG0
000001C0H 000001C4H
PRLH4[R/W]B,H,W PRLL4[R/W]B,H,W PRLH5[R/W]B,H,W PRLL5[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PRLH6[R/W]B,H,W PRLL6[R/W]B,H,W PRLH7[R/W]B,H,W PRLL7[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PPGC4[R/W] B,H,W 0000000X TRG1[R/W] B,H,W 00000000 PPGC5[R/W] B,H,W 0000000X PPGC6[R/W] B,H,W 0000000X REVC1[R/W] B,H,W 00000000 PPGC7[R/W] B,H,W 0000000X -
000001C8H 000001CCH 000001D0H
000001D4H 000001D8H
PRLH8[R/W]B,H,W PRLL8[R/W]B,H,W PRLH9[R/W]B,H,W PRLL9[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PRLHA[R/W]B,H,W PRLLA[R/W]B,H,W PRLHB[R/W]B,H,W PRLLB[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PPGC8[R/W] B,H,W 0000000X PRLHC[R/W] B,H,W XXXXXXXX PPGC9[R/W] B,H,W 0000000X PRLLC[R/W]B,H,W XXXXXXXX PPGCA[R/W] B,H,W 0000000X PRLHD[R/W] B,H,W XXXXXXXX PPGCB[R/W] B,H,W 0000000X PRLLD[R/W]B,H,W XXXXXXXX (Continued) PPG1
000001DCH
000001E0H
34
MB91220/S Series
Address 000001E4H
Register +0 +1 +2 +3 PRLHE[R/W]B,H,W PRLLE[R/W]B,H,W PRLHF[R/W]B,H,W PRLLF[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PPGCC[R/W] B,H,W 0000000X PPGCD[R/W] B,H,W 0000000X DMACA0[R/W] B,H,W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0[R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1[R/W] B,H,W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1[R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2[R/W] B,H,W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2[R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3[R/W] B,H,W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3[R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4[R/W] B,H,W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4[R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX Reserved DMACR[R/W] B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX PPGE[R/W]B,H,W 0000000X PPGCF[R/W] B,H,W 0000000X -
Block
000001E8H 000001ECH 000001F0H to 000001FCH 00000200H 00000204H 00000208H 0000020CH 00000210H 00000214H 00000218H 0000021CH 00000220H 00000224H 00000228H to 0000023CH 00000240H 00000244H to 000003ECH
PPG1
Reserved
DMAC
Reserved (Continued)
35
MB91220/S Series
Address 000003F0H 000003F4H 000003F8H 000003FCH 00000400H 00000404H 00000408H 0000040CH 00000410H 00000414H to 0000041CH 00000420H 00000424H 00000428H 0000042CH 00000430H 00000434H to 0000043CH 00000440H 00000444H 00000448H 0000044CH
Register +0 +1 +2 +3 BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0[R/W] B,H,W DDR1[R/W] B,H,W DDR2[R/W] B,H,W DDR3[R/W] B,H,W 00000000 00000000 00000000 00000000 DDR4[R/W] B,H,W DDR5[R/W] B,H,W DDR6[R/W] B,H,W DDR7[R/W] B,H,W 00000000 00000000 00000000 ----0000 DDR8[R/W] B,H,W DDR9[R/W] B,H,W DDRA[R/W] B,H,W DDRB[R/W] B,H,W 00000000 00000000 ----0000 00000000 DDRC[R/W] B,H,W DDRD[R/W] B,H,W DDRE[R/W] B,H,W DDRF[R/W] B,H,W ----0000 1111---00000000 00000000 DDRG[R/W] B,H,W ----0000 -
Block
Bit Search
Data Direction Register
PFR0[R/W] B,H,W 00000000 PFR4[R/W] B,H,W 00000000 PFR8[R/W] B,H,W 00000000 PFR1[R/W] B,H,W 00000000 PFR5[R/W] B,H,W 00000000 PFR9[R/W] B,H,W 00000000 PFR2[R/W] B,H,W 00000000 Reserved PFRA[R/W] B,H,W ----0000 PFR3[R/W] B,H,W 00000000 PFR7[R/W] B,H,W ----0000
Reserved
PFRB[R/W] B,H,W Port Function Register 00000000 PFRF[R/W] B,H,W 00000000 -
PFRC[R/W] B,H,W PFRD[R/W] B,H,W PFRE[R/W] B,H,W ----0000 00000000 00000000 PFRG[R/W] B,H,W ----0000 -
ICR00[R/W] B,H,W ICR01[R/W] B,H,W ICR02[R/W] B,H,W ICR03[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR04[R/W] B,H,W ICR05[R/W] B,H,W ICR06[R/W] B,H,W ICR07[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR08[R/W] B,H,W ICR09[R/W] B,H,W ICR10[R/W] B,H,W ICR11[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR12[R/W] B,H,W ICR13[R/W] B,H,W ICR14[R/W] B,H,W ICR15[R/W] B,H,W ---11111 ---11111 ---11111 ---11111
Reserved
Interrupt Control Unit
(Continued) 36
MB91220/S Series
Address 00000450H 00000454H 00000458H 0000045CH 00000460H 00000464H 00000468H 0000046CH 00000470H to 0000047CH 00000480H
Register +0 +1 +2 +3 ICR16[R/W] B,H,W ICR17[R/W] B,H,W ICR18[R/W] B,H,W ICR19[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR20[R/W] B,H,W ICR21[R/W] B,H,W ICR22[R/W] B,H,W ICR23[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR24[R/W] B,H,W ICR25[R/W] B,H,W ICR26[R/W] B,H,W ICR27[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR28[R/W] B,H,W ICR29[R/W] B,H,W ICR30[R/W] B,H,W ICR31[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR32[R/W] B,H,W ICR33[R/W] B,H,W ICR34[R/W] B,H,W ICR35[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR36[R/W] B,H,W ICR37[R/W] B,H,W ICR38[R/W] B,H,W ICR39[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR40[R/W] B,H,W ICR41[R/W] B,H,W ICR42[R/W] B,H,W ICR43[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 ICR44[R/W] B,H,W ICR45[R/W] B,H,W ICR46[R/W] B,H,W ICR47[R/W] B,H,W ---11111 ---11111 ---11111 ---11111 RSRR [R/W] B,H,W STCR [R/W] B,H,W TBCR [R/W] B,H,W 10000000 00110011 00XXXX11 CLKR [W] B,H,W 00000000 WPR [R/W] B,H,W XXXXXXXX DIVR0 [R/W] B,H,W 00000011 OSCCR [R/W] B X000XXX0 Reserved OSCR [R/W] B 000--001 Reserved CTBR [W] B,H,W XXXXXXXX DIVR1 [R/W] B,H,W 00000000 -
Block
Interrupt Control Unit
Reserved
00000484H
Clock Control Unit
00000488H 0000048CH 00000490H 00000494H to 000004ACH
Clock Control Unit
Reserved (Continued)
37
MB91220/S Series
Address
Register +0 PRLHG[R/W] B,H,W 00000000 PRLHI[R/W]B,H,W 00000000 PPGCG[R/W] B,H,W 0000000X +1 TRG2[R/W] B,H,W 00000000 PRLLG[R/W]B,H,W XXXXXXXX +2 PRLHH[R/W] B,H,W XXXXXXXX +3 REVC2[R/W] B,H,W 00000000 PRLLH[R/W]B,H,W XXXXXXXX
Block
000004B0H
00000B4H
000004B8H
PRLLI[R/W]B,H,W PRLHJ[R/W]B,H,W PRLLJ[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX PPGCH[R/W] B,H,W 0000000X PPGCI[R/W]B,H,W PPGCJ[R/W]B,H,W 0000000X 0000000X
000004BCH
PPG2
000004C0H
PRLHK[R/W]B,H,W PRLLK[R/W]B,H,W PRLHL[R/W]B,H,W PRLLL[R/W]B,H,W 00000000 XXXXXXXX XXXXXXXX XXXXXXXX PRLHM[R/W] B,H,W 00000000 PPGCK[R/W] B,H,W 0000000X PRLLM[R/W]B,H,W XXXXXXXX PPGCL[R/W] B,H,W 0000000X TRG3[R/W] B,H,W 00000000 PRLHO[R/W] B,H,W 00000000 PRLHQ[R/W] B,H,W 00000000 PPGCO[R/W] B,H,W 0000000X REVC3[R/W] B,H,W 00000000 PRLHN[R/W] B,H,W XXXXXXXX PPGCM[R/W] B,H,W 0000000X PRLLN[R/W]B,H,W XXXXXXXX PPGCN[R/W] B,H,W 0000000X
000004C4H
000004C8H 000004CCH 000004D0H
000004D4H
PRLLO[R/W]B,H,W PRLHP[R/W]B,H,W PRLLP[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX PRLLQ[R/W]B,H,W XXXXXXXX PPGCP[R/W] B,H,W 0000000X PRLHR[R/W] B,H,W XXXXXXXX PPGCQ[R/W] B,H,W 0000000X PRLLR[R/W]B,H,W XXXXXXXX PPGCR[R/W] B,H,W 0000000X
000004D8H
000004DCH
PPG3
000004E0H
PRLHS[R/W]B,H,W PRLLS[R/W]B,H,W PRLHT[R/W]B,H,W PRLLT[R/W]B,H,W 00000000 XXXXXXXX XXXXXXXX XXXXXXXX PRLHU[R/W] B,H,W 00000000 PPGCS[R/W] B,H,W 0000000X PRLLU[R/W]B,H,W PRLHV[R/W]B,H,W PRLLV[R/W]B,H,W XXXXXXXX XXXXXXXX XXXXXXXX PPGCT[R/W] B,H,W 0000000X (Continued) PPGCU[R/W] B,H,W 0000000X PPGCV[R/W] B,H,W 0000000X
000004E4H
000004E8H 000004ECH
38
MB91220/S Series
Address 000004F0H to 000004F8H 000004FCH 00000500H to 0000053CH 00000540H 00000544H 00000548H 0000054CH 00000550H 00000554H to 0000055CH 00000560H
Register +0 +1 PSCR[W] B XXXXXXXX +2 +3
Block
Reserved Port Input Level Select Register Reserved Reserved Reserved Reserved Port Input Level Select Register
-
-
-
PILR0[R/W] B 00000000 PILR4[R/W] B 00000000 PILR1[R/W] B 00000000 PILR5[R/W] B 00000000 IBCR0[R/W] B,H,W 00000000 ITMKH0[R/W] B,H,W 00----11 IBCR1[R/W] B,H,W 00000000 ITMKH1[R/W] B,H,W 00----11 IBSR0[R] B,H,W 00000000 ITMKL0[R/W] B,H,W 11111111 ITBAH0[R/W] B,H,W ------00 ITBAL0[R/W] B,H,W 00000000 PILRE[R/W] B 00000000 Reserved
Reserved
00000564H 00000568H 0000056CH
ISMK0[R/W] B,H,W ISBA0[R/W] B,H,W 01111111 -0000000
I2C0
IDAR0[R/W] B,H,W ICCR0[R/W] B,H,W IDBL0[R/W] B,H,W 00000000 -0011111 -------0 IBSR1[R] B,H,W 00000000 ITMKL1[R/W] B,H,W 11111111 ITBAH1[R/W] B,H,W ------00 ITBAL1[R/W] B,H,W 00000000 I2C1
00000570H 00000574H 00000578H 0000057CH 00000580H to 000005FCH
ISMK1[R/W] B,H,W ISBA1[R/W] B,H,W 01111111 -0000000
IDAR1[R/W] B,H,W ICCR1[R/W] B,H,W IDBL1[R/W] B,H,W 00000000 -0011111 -------0 Reserved Reserved Reserved Detection of CPU operation Reserved (Continued) 39
Reserved
LVRC[R/W] B,H,W 00011000 -
MB91220/S Series
Address
Register +0 Reserved EPFR4[R/W] B,H,W 11111111 EPFR8[R/W] B,H,W 00000000 EPFRG[R/W] B,H,W ----0000 +1 Reserved EPFR5[R/W] B,H,W 00000000 EPFR9[R/W] B,H,W 00000000 EPFRD[R/W] B,H,W 00000000 +2 EPFR2[R/W] B,H,W 00000000 +3 EPFR3[R/W] B,H,W 00000000 EPFR7[R/W] B,H,W ----0000 EPFRF[R/W] B,H,W 00000000 -
Block
00000600H
00000604H
00000608H
EPFRE[R/W] B,H,W 00000000 -
I/O port
0000060CH
00000610H 00000614H to 0000063CH 00000640H 00000644H 00000648H 0000064CH 00000650H to 0000065CH 00000660H 00000664H 00000668H to 0000067CH 00000680H 00000684H to 000007F8H 000007FCH
ASR0 [R/W] B,H,W 00000000 00000000 ASR1 [R/W] B,H,W XXXXXXXX XXXXXXXX ASR2 [R/W] B,H,W XXXXXXXX XXXXXXXX ASR3 [R/W] B,H,W XXXXXXXX XXXXXXXX Reserved AWR0 [R/W] B,H,W 01111111 11111111 AWR2 [R/W] B,H,W XXXXXXXX XXXXXXXX Reserved CSER[R/W] B,H,W XXXX0001 AWR1 [R/W] B,H,W XXXXXXXX XXXXXXXX AWR3 [R/W] B,H,W XXXXXXXX XXXXXXXX ACR0 [R/W] B,H,W 1111XX00 00000000 ACR1 [R/W] B,H,W XXXXXXXX XXXXXXXX ACR2 [R/W] B,H,W XXXXXXXX XXXXXXXX ACR3 [R/W] B,H,W XXXXXXXX XXXXXXXX
Reserved
T-unit
-
-
-
MODR * -
Reserved (Continued)
40
MB91220/S Series
Address 00000800H to 00000FFCH 00001000H 00001004H 00001008H 0000100CH 00001010H 00001014H 00001018H 0000101CH 00001020H 00001024H 00001028H to 00006FFCH 00007000H 00007004H 00007008H to 0000FFFCH 00020000H 00020004H
Register +0 +1 +2 Reserved DMASA0[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved FLCR[R/W] 01XX1000 FLWC[R/W] 00000011 +3
Block
DMAC
-
-
Flash I/F -
Reserved CTRLR0 00000000 00000001 ERRCNT0 00000000 00000000 INTR0 00000000 00000000 BRPER0 00000000 00000000 STATR0 00000000 00000000 BTR0 00100011 00000001 TESTR0 00000000 r0000000* (r : indication the level on the CAN bus) Reserved (Continued) 41 CAN0
00020008H
0002000CH
MB91220/S Series
Address 00020010H 00020014H 00020018H 0002001CH 00020020H 00020024H 00020028H to 0002002CH 00020030H 00020034H 00020038H to 0002003CH 00020040H 00020044H 00020048H 0002004CH 00020050H 00020054H 00020058H to 0002005CH 00020060H 00020064H
Register +0 +1 +2 +3 IF1CREQ0 00000000 00000001 IF1MSK20 11111111 11111111 IF1ARB20 00000000 00000000 IF1MCTR0 00000000 00000000 IF1DTA10 00000000 00000000 IF1DTB10 00000000 00000000 Reserved IF1DTA20 00000000 00000000 IF1DTB20 00000000 00000000 Reserved IF2CREQ0 00000000 00000001 IF2MSK20 00000000 00000000 IF2ARB20 00000000 00000000 IF2MCTR0 00000000 00000000 IF2DTA10 00000000 00000000 IF2DTB10 00000000 00000000 Reserved IF2DTA20 00000000 00000000 IF2DTB20 00000000 00000000 IF2DTA10 00000000 00000000 IF2DTB10 00000000 00000000 IF2CMSK0 00000000 00000000 IF2MSK10 00000000 00000000 IF2ARB10 00000000 00000000 IF2DTA20 00000000 00000000 IF2DTB20 00000000 00000000 IF1DTA10 00000000 00000000 IF1DTB10 00000000 00000000 IF1CMSK0 00000000 00000000 IF1MSK10 11111111 11111111 IF1ARB10 00000000 00000000 IF1DTA20 00000000 00000000 IF1DTB20 00000000 00000000
Block
CAN0
(Continued) 42
MB91220/S Series
Address 00020068H to 0002007CH 00020080H 00020084H to 0002008CH 00020090H 00020094H to 0002009CH 000200A0H 000200A4H to 000200ACH 000200B0H 000200B4H to 000200BCH 00020100H 00020104H 00020108H 0002010CH 00020110H 00020114H 00020118H
Register +0 +1 Reserved TREQR10 00000000 00000000 Reserved NEWDT10 00000000 00000000 Reserved INTPEND10 00000000 00000000 Reserved MESVAL10 00000000 00000000 Reserved CTRLR1 00000000 00000001 ERRCNT1 00000000 00000000 INTR1 00000000 00000000 BRPER1 00000000 00000000 IF1CREQ1 00000000 00000001 IF1MSK21 11111111 11111111 IF1ARB21 00000000 00000000 STATR1 00000000 00000000 BTR1 00100011 00000001 TESTR1 00000000 r0000000* Reserved IF1CMSK1 00000000 00000000 IF1MSK11 11111111 11111111 IF1ARB11 00000000 00000000 +2 +3
Block
Reserved
Reserved
CAN0
Reserved
Reserved
CAN1
(Continued)
43
MB91220/S Series
Address 0002011CH 00020120H 00020124H 00020128H to 0002012CH 00020130H 00020134H 00020138H to 0002013CH 00020140H 00020144H 00020148H 0002014CH 00020150H 00020154H 00020158H to 0002015CH 00020160H 00020164H 00020168H to 0002017CH 00020180H
Register +0 +1 +2 IF1DTA21 00000000 00000000 IF1DTB21 00000000 00000000 Reserved IF1DTA21 00000000 00000000 IF1DTB21 00000000 00000000 Reserved IF2CREQ1 00000000 00000001 IF2MSK21 00000000 00000000 IF2ARB21 00000000 00000000 IF2MCTR1 00000000 00000000 IF2DTA11 00000000 00000000 IF2DTB11 00000000 00000000 Reserved IF2DTA21 00000000 00000000 IF2DTB21 00000000 00000000 Reserved TREQR11 00000000 00000000 IF2DTA11 00000000 00000000 IF2DTB11 00000000 00000000 IF2CMSK1 00000000 00000000 IF2MSK11 00000000 00000000 IF2ARB11 00000000 00000000 IF2DTA21 00000000 00000000 IF2DTB21 00000000 00000000 IF1DTA11 00000000 00000000 IF1DTB11 00000000 00000000 +3 IF1MCTR1 00000000 00000000 IF1DTA11 00000000 00000000 IF1DTB11 00000000 00000000
Block
CAN1
Reserved
(Continued)
44
MB91220/S Series
(Continued) Address 00020184H to 0002018CH 00020190H 00020194H to 0002019CH 000201A0H 000201A4H to 000201ACH 000201B0H 000201B4H to 000201BCH Reserved Reserved Reserved Register +0 +1 Reserved NEWDT11 00000000 00000000 Reserved INTPEND11 00000000 00000000 Reserved MESVAL11 00000000 00000000 Reserved +2 +3 Block
CAN1
* : The lower 16 bits (DTC [15 : 0] ) of DMCA0 to DMCA4 cannot be accessed in bytes. Notes : * Do not perform read modify write instructions to a register including write-on-bit. * The data in the area reserved or - is undefined.
45
MB91220/S Series
VECTOR TABLE
Interrupt number Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (ICE) Undefined instruction exception NMI instruction External interrupt 0/1/2/6/7 External interrupt 3 External interrupt 4 External interrupt 5 PPG0H/0L/8H/8L PPG2H/2L/9H/9L PPG4H/4L/10H/10L PPG6H/6L/11H/11L Reload timer 0 Reload timer 1 Reload timer 2 LIN-UART0 (Reception) LIN-UART0 (Transmission) LIN-UART1 (Reception) LIN-UART1 (Transmission) LIN-UART2 (Reception) LIN-UART2 (Transmission) LIN-UART3 (Reception) LIN-UART3 (Transmission) Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 Interrupt level 0FH Fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H 374H TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H DMA start source 6 7 8 9 10 1 4 2 5 (Continued) 46
MB91220/S Series
(Continued) Interrupt number Interrupt source CAN0 CAN1 PPG12H/12L/I C0 PPG13H/13L PPG14H/14L/I C1 PWC (Measurement completed) PWC (Overflow) DMAC A/D converter Real-time clock PPG15H/15L Main oscillation stabilization wait timer Timebase timer overflow PPG1H/1L PPG3H/3L PPG5H/5L PPG7H/7L 16-bit free-run timer 0 16-bit free-run timer 1 ICU0 ICU1 ICU2 ICU3 OCU0 OCU1 Sound generator 0 Sound generator 1 Sound generator 2 Delay interrupt System reserved System reserved System reserved
2 2
Decimal 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 to 79 80 to 255
Hexadecimal 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 to 4F 50 to FF
Interrupt level ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H to 2C0H 2BCH to 000H
TBR default address 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H to 000FFEC0H 000FFEBCH to 000FFC00H
DMA start source 14 11 12 13 3
INT instruction
47
MB91220/S Series
TABLE OF PIN STATUS IN EACH MODE
* Single chip mode Initial value Pin Name INITX X0 Main clock X1 X0A Sub clock X1A MD0 MD1 MD2 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31/ATGX SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 (Continued) Output Hi-Z Input cut-off Output Hi-Z Previous Previous Input state held state held permitted Output Hi-Z Input cut-off When LCD is used, output operation or output retention for both SLEEP/STOP Output Hi-Z Input cut-off Output Hi-Z Previous Previous Input state held state held permitted Output Hi-Z Input cut-off When LCD is used, output operation or output retention for both SLEEP/STOP Mode Input permitted Input Input Input permitted permitted permitted Function name INITX=L INITX=H In SLEEP State INIT Input permitted Hi-Z or Input permitted "H" output or input permitted Hi-Z or input permitted "H" output or input permitted In STOP State HIZ=0 HIZ=1 Remarks
48
MB91220/S Series
Initial value Pin Name P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 Function name INITX=L INITX=H
In SLEEP State
In STOP State HIZ=0 HIZ=1 Remarks
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SIN0/INT0 SOT0 SCK0 SIN3/INT1 SOT3 SCK3 SIN4/CK0 SOT4 SCK4 SIN5/CK1 SOT5 SCK5 OUT0 OUT1 (Continued) Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off Input of external interrupt is enabled by setting PFR Output Hi-Z Input cut-off Output Hi-Z Previous Previous Input state held state held permitted Output Hi-Z Input cut-off When LCD is used, output operation or output retention for both SLEEP/STOP Output Hi-Z Input cut-off Output Hi-Z Previous Previous Input state held state held permitted Output Hi-Z Input cut-off When LCD is used, output operation or output retention for both SLEEP/STOP
49
MB91220/S Series
Initial value Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0 PA1 PA2 PA3 Function name INITX=L INITX=H
In SLEEP State
In STOP State HIZ=0 HIZ=1 Remarks
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 INT60/RX0 TX0 INT7/RX1 TX1 AN16 AN17 AN18 AN19 AN20/INT2 AN21/INT3 AN22/INT4 AN23/INT5 DA0 DA1 SGA0 SGO0 SGA1 SGO1 SGA2 SGO2 PWM1P3 PWM1M3 PWM2P3 PWM2M3 Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off (Continued) Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input Previous Previous Input permitted state held state held permitted Output Hi-Z Input cut-off Input of external interrupt is enabled by setting PFR Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input cut-off
Previous Previous state held state held
Previous Previous state held state held
When DA is used, output retention
50
MB91220/S Series
Initial value Pin Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Function name INITX=L INITX=H
In SLEEP State
In STOP State HIZ=0 HIZ=1 Remarks
PPG8H PPG9H PPG10H PPG11H PWM1P1 PWM1M1 PWM2P1 PWM2M1 PWM1P0 PWM1M0 PWM2P0 PWM2M0 TIN0/IN0/PWC0/INT2/V0 TIN1/IN1/V1 TIN2/IN2/V2 IN3/V3 COM0/PPG1H COM1/PPG3H COM2/PPG5H COM3/PPG7H PWM1P2 PWM1M2 PWM2P2 PWM2M2 PPG12H/SDA0 PPG13H/SCL0 PPG14H/SDA1 PPG15H/SCL1 (Continued) Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off "L" output "L" output Previous Input Input state held permitted permitted Input Input Previous permitted permitted state held Previous state held Output Hi-Z Input cut-off Input of external interrupt is enabled by setting PFR When LCD is used, output operation or output retention for both SLEEP/STOP Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off
51
MB91220/S Series
(Continued) Initial value Pin Name PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 Function name INITX=L INITX=H In SLEEP State AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 PPG0H TOT0/PPG2H TOT1/PPG4H TOT2/PPG6H Output Output Hi-Z Previous Previous Hi-Z Input state held state held Input permitted permitted Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input cut-off In STOP State HIZ=0 HIZ=1 Remarks
Previous Previous state held state held
52
MB91220/S Series
* External bus mode (8-bit) Initial value Pin Name INITX X0 Main clock X1 X0A Sub clock X1A MD0 MD1 MD2 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31/ATGX D08 D09 D10 D11 D12 D13 D14 D15 A00 A01 A02 A03 A04 A05 A06 A07 (Continued) 53 Output Hi-Z Input cut-off Output Hi-Z Input permitted Address output Address output Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input permitted Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Previous Previous Input state held state held permitted Output Hi-Z Input cut-off When LCD is used, output operation or output retention for both SLEEP/STOP Mode Input permitted Input Input Input permitted permitted permitted Function name INIT INITX=L INITX=H In SLEEP State Input permitted Hi-Z or Input permitted "H" output or input permitted Hi-Z or Input permitted "H" output or input permitted In STOP State HIZ=0 HIZ=1 Remarks
Hi-Z
Hi-Z
No port function
No port function
MB91220/S Series
(Continued) Initial value Pin Name P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 to PG3 Function name INITX=L INITX=H In SLEEP State A08 A09 A10 A11 A12 A13 A14 A15 SIN0/INT0 SOT0 SCK0 SIN3/INT1 SOT3 SCK3 ASX SYSCLK SIN4/CK0/CS0X SOT4/CS1X SCK4/CS2X SIN5/CK1/CS3X SOT5/RDX SCK5/WR0X OUT0 OUT1/RDY Input permitted It is the same as the single chip. Output Hi-Z Input permitted Output Hi-Z Input Previous Previous permitted state held state held Output Hi-Z Input cut-off When external bus signal is used, "H" output for SLEEP/ STOP (Hi-Z=0) Output Hi-Z Input permitted Output Hi-Z Input permitted Previous Previous state held state held "H" output Clock output Input of external interrupt is enabled by setting PFR When external bus signal is used, "H" output/clock output for SLEEP/STOP (Hi-Z=0) Output Hi-Z Input cut-off Output Hi-Z Input permitted Output Hi-Z Input cut-off In STOP State HIZ=0 HIZ=1 Remarks
Address output
Address output
No port function
Output Hi-Z Input cut-off
54
MB91220/S Series
* External bus mode (16-bit) Initial value Pin Name INITX X0 X1 X0A X1A MD0 MD1 MD2 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 A00 A01 A02 A03 A04 A05 A06 A07 (Continued) 55 Output Hi-Z Input cut-off Output Hi-Z Input permitted Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input permitted Output Hi-Z Input cut-off Output Hi-Z Input cut-off Output Hi-Z Input permitted Output Hi-Z Input cut-off Mode Input permitted Sub clock Main clock Input permitted Input permitted Input permitted Function name INITX=L INITX=H In SLEEP State INIT Input permitted Hi-Z or Input permitted "H" output or input permitted Hi-Z or Input permitted "H" output or input permitted In STOP State HIZ=0 HIZ=1 Remarks
Hi-Z
Hi-Z
No port function
Hi-Z
Hi-Z
No port function
Address output
Address output
No port function
MB91220/S Series
(Continued) Initial value Pin Name P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 to PG3 Function name INITX=L INITX=H In SLEEP State A08 A09 A10 A11 A12 A13 A14 A15 SIN0/INT0 SOT0 SCK0 SIN3/INT1 SOT3 SCK3 ASX SYSCLK SIN4/CK0/CS0X SOT4/CS1X SCK4/CS2X SIN5/CK1/CS3X SOT5/RDX SCK5/WR0X OUT0/WR1X OUT1/RDY Input permitted It is the same as the single chip. Output Hi-Z Input permitted Output Hi-Z Input Previous Previous permitted state held state held Output Hi-Z Input cut-off When external bus signal is used, "H" output for SLEEP/ STOP (Hi-Z=0) Output Hi-Z Input permitted Output Hi-Z Input permitted Previous Previous state held state held "H" output Clock output Input of external interrupt is enabled by setting PFR When external bus signal is used, "H" output/clock output for SLEEP/STOP (Hi-Z=0) Output Hi-Z Input cut-off Output Hi-Z Input permitted Output Hi-Z Input cut-off In STOP State HIZ=0 HIZ=1 Remarks
Address output
Address output
No port function
Output Hi-Z Input cut-off
56
MB91220/S Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage*1 AVCC VAVRH DVCC Input voltage*1 Output voltage*
1
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 6.0 VCC + 6.0 15 40 4 30 120 330 50 160 -15 -40 -4 -30 -120 -330 -50 -160 660 +105 +85 +150 +2
Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C C mA AVCC = VCC*2 AVCC VAVRH DVCC = VCC*2 *9 *9 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6
Remarks
VI VO IOL1 IOL2 IOLAV1 IOLAV2 IOL1 IOL2 IOLAV1 IOLAV2 IOH1*
3
"L" level maximum output current*3 "L" level average output current*4 "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature +B input standard (Maximum clamp current) +B input standard (Total maximum clamp current)
IOH2*3 IOHAV1*4 IOHAV2* IOH1 IOH2 IOHAV1* PD TA Tstg ICLAMP
7 4
-40 -40 -55 -2
IOHAV2*7
In single chip operation In external bus operation Except dedicated input pins, (PD3 to PD0) and D/AC output pins (P91, P90) *8
ICLAMP
-20
+20
mA (Continued)
57
MB91220/S Series
(Continued) *1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V. *2 : Note that AVCC and DVCC should not exceed VCC upon power-on and under other circumstances. *3 : The maximum output current defines the peak current value of each of the corresponding pins. *4 : The average output current defines the average value of the current (100 ms) which passes through each of the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *5 : Output other than PA0 to PA3 pins, PB4 to PB7 pins, PC0 to PC3 pins, and PE0 to PE3 pins. *6 : (PA0 to PA3, PE0 to PE3) + (PB4 to PB7, PC0 to PC3) . The stepping motor controller pins are divided into two groups (8 pins each) and the value is calculated as the total current per group. *7 : The total average output current defines the average value of the current (100 ms) which passes through all the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *8 : +B input standard defines the current value for each of the corresponding pins. *9 : VI and VO should not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, when the +B input-enabled pin is used the ICLAMP rating supersedes the VI rating. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Recommended example circuit
MB91220/S series
Protection diode
lIHH
+B Input (12 V to 16 V) Current limiting resistor
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
58
MB91220/S Series
2. Recommended Operating Conditions
(VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Rating Min 4.5 Power supply voltage VCC AVCC DVCC 3.5 2.0 Max 5.5 5.5 5.5 Unit V V V F +105 +85 C C Remarks Recommended guaranteed operating range Guaranteed operating range*1 Guaranteed operating range for holding stop operation status*2 (MB91F223/S) Use a ceramic capacitor or a capacitor with similar frequency characteristics. In single chip operation In external bus operation
Smoothing capacitor*3 Operating temperature
CS TA -40 -40
1
*1 : Exclusive of A/D and D/A operation *2 : Internal voltage held in RAM : 1.8 V (Min) /3.6 V (Max) *3 : For how to connect the smoothing capacitor CS, refer to the diagram below. * C Pin Connection Diagram
VCC3C
CS
VSS
DVSS
AVSS
< + B input (12 V to 16 V) conditions> * Do not connect +B potential directly to a microcontroller pin. * Always connect a resistor between the microcontroller pin and +B signal to limit the current. lIHH = 2 mA per pin (Max.) [In the steady state and transient state between power-on and power-off, etc.] It can be connected to any general-purpose input port except the output pin for LCDC. * The protection diode in the microcontroller turns the potential upon +B input between the limiting resistor and microcontroller pin into "VCC + protection diode ON voltage". Configure the circuit so that these are not interfered and the potential is not exceeded.
59
MB91220/S Series
3. DC Specifications
(TA : - 40 C to + 105 C ;Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin name P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P73, P80 to P87, P90 to P97, PA0 to PA3, PB0 to PB7, PC0 to PC3, PD0 to PD7, PE0 to PE7, PF0 to PF7, PG0 to PG3 P40, P43, P50, P53 PE4 to PE7 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P57, P60 to P67, PF0 to PF7 X0, X1, X0A, X1A, INITX P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P73, P80 to P87, P90 to P97, PA0 to PA3, PB0 to PB7, PC0 to PC3, PD0 to PD7, PE0 to PE7, PF0 to PF7, PG0 to PG3 P40, P43, P50, P53, PE4 to PE7 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P57, P60 to P67, PF0 to PF7 MD0 to MD2 X0, X1, X0A, X1A, INITX Condition Value Min Typ Max Unit Remarks
VIHS
0.8 VCC
VCC + 0.3
V
Automotive level input pins*1
"H" level input voltage
VIH
0.7 VCC
VCC + 0.3
V
CMOS input pins*2
VIHT

2.0 VCC - 0.3 0.8 VCC

VCC + 0.3 VCC + 0.3
V
TTL input pins*4
VIHM MD0 to MD2 VIHX
V V
MD pins*3
VILS
VSS - 0.3
0.5 VCC
V
Automotive level input pins*1
"L" level input voltage
VIL
VSS - 0.3
0.3 VCC
V
CMOS hysteresis input pins*2
VILT

VSS - 0.3 VSS - 0.3

0.8 Vss + 0.3 0.2 VCC
V
TTL input pins*4
VILM VILX
V V
MD pins*3 (Continued)
60
MB91220/S Series
(TA : - 40 C to + 105 C; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol ICC Pin name Condition Value Min Typ 85 135 40 Max 105 155 70 Unit mA Remarks Under normal operation
Operating frequency : FCP = 32 MHz in main mode Operating frequency : FCP = 32 MHz in main sleep mode Operating frequency : FCP = 32 kHz, TA = +25 C in sub mode Operating frequency : FCP = 32 kHz, TA = +25 C, Vcc = 5V in sub sleep mode TA = +25 C, Vcc = 5V in stop mode (oscillation stopped) TA = +25 C, Vcc = 5V in stop mode (RTC in use*8) Sub clock frequency : FCP = 32 kHz, TA = +25 C, Vcc = 5V in stop mode (Real Time Clock Operation*8) All input pins Other than VCC, VSS, DVCC, DVSS, AVCC, AVSS, PA0 to PA3, PB4 to PB7, PC0 to PC3, PE0 to PE3 PA0 to PA3, PB4 to PB7, PC0 to PC3, PE0 to PE3 INITX VCC = DVCC = AVCC = 5.5 V VSS < VI < VCC
mA In Flash-Write mode mA
ICCS
ICCL
200
450
A
main oscillation/ PLL stops*6
Power supply current*5
ICCLS
VCC
180
400
A
main oscillation/ PLL stops*6 main clock/PLL/ sub-oscillation halted*7 PLL/ sub-oscillation halted*7 main oscillation/ PLL stops*6
ICCH
10
150
A
ICTS4M
330
500
A
ICTS32K
40
180
A
Input leak current
IIL
-5
+5
A
Input capacity 1
CIN1
5
15
pF
Input capacity 2 Pull-up resistance
CIN2
15
45
pF
RUP
25
50
100
k (Continued)
61
MB91220/S Series
(TA : - 40 C to + 105 C; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin name Other than PA0 to PA3, PB4 to PB7, PC0 to PC3, PE0 to PE3 PA0 to PA3, PB4 to PB7, PC0 to PC3, PE0 to PE3 Other than PA0 to PA3, PB4 to PB7, PC0 to PC3, PE0 to PE3 PA0 to PA3, PB4 to PB7, PC0 to PC3, PE0 to PE3 Condition Value Min VCC - 0.5 Typ Max Unit Remarks
Output "H" voltage 1
VOH1
Vcc = 4.5 V IOH = -4.0 mA
V
Output "H" voltage 2
VOH2
Vcc = 4.5 V IOH = -30.0 mA
VCC - 0.5
V
Output "L" voltage 1
VOL1
Vcc = 4.5 V IOL = 4.0 mA
0.4
V
Output "L" voltage 2
VOL2
Vcc = 4.5 V IOL = 30.0 mA Vcc = 4.5 V IOH = 30.0 mA Maximum deviation of VOH2 Vcc = 4.5 V IOL = 30.0 mA Maximum deviation of VOL2 TA = +25 C
0.55
V
PWM1Pn, High current output PWM1Mn, Drive capacity VOH2 PWM2Pn, Phase-to-phase PWM2Mn, deviation 1 n = 0 to 3 High current output Drive capacity Phase-to-phase deviation 2 COM0 to COM3 Output impedance SEG00 to SEG31 Output impedance LCDC leak current PWM1Pn, PWM1Mn, VOL2 PWM2Pn, PWM2Mn, n = 0 to 3 RVCOM COM0 to COM3 RVSEG SEG0 to SEG31 ILCDC COM0 to COM3, SEG0 to SEG31
0
90
mV *9
0
90
mV *9
-0.5

4.5 30 +0.5
k k A
*1 : All input pins except X0, X1, X0A, X1A, MD0, MD1, MD2 and INITX pins *2 : CMOS input can be switched by the SIN of the LIN-UART and I2C input pin and switched by the input level selection register (PILR) . *3 : MD0, MD1, MD2 *4 : TTL input can be selected by the external bus input pins and input pin only in the parallel writer mode. The external bus input pins (P00 to P17 and P57) can be switched by the input level selection register (PILR) . *5 : They represent current values used when supplying power to the external clock from pin X1. (Continued)
62
MB91220/S Series
(Continued) *6 : Before switching from the main clock operation mode to the sub clock operation (operation in sub RUN, sub SLEEP, and sub RTC) mode, set the main oscillation stop bit (OSCDS1) in the oscillation control register (OSCCR) to "1" and the clock source to half of the source oscillation input, and then stop the PLL. *7 : Before switching from the main clock operation mode to the stop mode, set the clock source to half of the source oscillation input , stop the PLL, set the OSDC1 bit in the standby control register (STCR) to "1". However, if using the main clock RTC operation , set the clock source to half of the source oscillation input, stop the PLL, and then set each clock of the CPU clock (CLKB) , peripheral clock (CLKP) , and external interface clock (CLKT) to the division ratio of 8 or more using the base clock divide setting registers 0 and 1 (DIVR0 and 1) before switching to the stop mode. *8 : The real time clock can be operated only in the 4 MHz main clock oscillation or 32 kHz sub clock oscillation. *9 : Defined by the maximum deviation of VOH2/VOL2 of each pin, when PWM1P0, PWM1M0, PWM2P0 and PWM2M0 in ch.0 are simultaneously turned on. Other channels are applied in the same condition.
63
MB91220/S Series
4. Flash Memory Write/Erase Characteristics
Parameter Sector erase time Chip erase time Halfword write time Chip write time Erase/write cycle Flash memory data retain time Condition TA = +25 C, Vcc = 5.0 V TA = +25 C, Vcc = 5.0 V TA = +25 C, Vcc = 5.0 V TA = +25 C, Vcc = 5.0 V TA = +85 C (average) Value Min 10000 10 Typ 1 5 16 2.1 Max 15 3600 Unit s s s s cycle year * Remarks Exclusive of internal write time prior to erase Exclusive of internal write time prior to erase Exclusive of overhead time at system level Exclusive of overhead time at system level
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into average temperature at + 85 C) .
64
MB91220/S Series
5. AC Specifications
(1) Clock timing (TA : - 40 C to + 105 C; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V) Parameter Frequency of source oscillation clock Source oscillation clock cycle time Input clock pulse width Input clock rise/fall time Frequency of internal operating clock Internal operating clock cycle time CAN PLL cycle jitter (When locked) Symbol FC Fca tCYL PWH, PWL tcr, tcf FCP tCP Pin name X0, X1 X0A, X1A X0, X1 Condition Value Min 100 31.25 - 10 32 + 10 MHz ns FCP = 32 MHz (4 MHz, PLL multiplied by 8) Typ 4 32.768 250 Max 5 Unit MHz kHz ns The duty ratio normally ranges from 40% to 60%. When external clock is used Remarks
X0
ns
X0
ns
tPJ
ns
* X0/X1 Clock Timing
tCYL 0.8 VCC 0.2 VCC
X0
PWH
tcf
PWL
tcr
65
MB91220/S Series
* CAN PLL cycle jitter Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. PLL output
t1 t2 t3 tn-1 tn
Ideal clock Slow
t3 tn-1 tn
Deviation time
t1
t2
Fast
* Operations Oscillation should be performed as described below : [Source oscillation] : X0/X1 : 4 MHz, PLL : multiplied by 8, Internal frequency : 32 MHz : X0A/X1A : 32 kHz, PLL : no multiplication, Internal frequency : 32 kHz Note that the PLL oscillation stabilization wait time should be set to 500 s or more. Sample oscillation circuit
X0
X1
R
C1
C2
66
MB91220/S Series
AC specifications are defined by the following measurement standard voltage values : * Input signal wave form Automotive input pin
0.8 VCC 0.5 VCC
* Output signal wave form Output pin
2.4 V 0.8 V
CMOS input pin
0.7 VCC 0.3 VCC
TTL input pin
2.0 V 0.8 V
67
MB91220/S Series
(2) Reset input (TA : - 40 C to + 105 C; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin name Condition Value Min 500 INITX input time tINTL INITX Oscillation time of oscillator* + 10 tcp + 12 s Max Unit ns Remarks Under normal operation In stop mode
ms
* : The oscillation time of the oscillator refers to the time when the amplitude has reached 90%. The oscillation time of the crystal oscillator ranges from several ms to tens of ms. The oscillation time of the ceramic oscillator ranges from several hundreds to several ms, while that of the external clock is 0 ms.
tINTL
INITX
0.2 VCC 0.2 VCC
* In stop mode
tINTL
INITX
0.2 VCC 0.2 VCC
X0
90% of amplitude
Internal operation clock Oscillation time of oscillator Internal reset
10 tcp + 12 s
Oscillation stabilization wait time Instruction executed
68
MB91220/S Series
[External reset input specifications (INITX) and internal reset signal cancellation timing] * When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the internal reset signal to transmit all reset signals to the internal logic (Max 8 s at 32 MHz) . * The following chart shows how to set the timing for instruction execution start (start of application operation) after external reset input. Time from external reset input to instruction start = Max 256 tcp + 61 tcp * Timing Chart
INITX
Min 10 tcp
Internal reset input timing
61 tcp Max 256 tcp
Internal reset
Internal reset cancellation timing
[Pin state in external bus mode] In the external bus mode, it is not guaranteed to hold the RAM value upon external reset (INITX = "0") input. Beside that, the value of the internal bus is to be output to each pin during the time between the internal reset input and its cancellation. * Timing Chart (Pin State for External Bus Mode : 1)
INITX
Min 10 tcp
Internal reset
Max 256 tcp
61 tcp
Pin state of external bus
Hi-Z
Value immediately before reset
Initial value at reset
69
MB91220/S Series
It can be avoided by the following external reset input to continue Hi-Z. * Timing Chart (Pin State for External Bus Mode : 2)
INITX
256 tcp
Internal reset
Max 256 tcp
61 tcp
Pin state of external bus
Hi-Z
Initial value at reset
70
MB91220/S Series
(3) Power-on Conditions (TA : - 40 C to + 105 C; VSS = 0.0 V) Parameter Power supply rising time Power supply start voltage Power supply peak voltage Power supply cut-off time Symbol Pin name tR VOFF VCC VON tOFF 2.7 50 V ms Due to the repetitive operation Condition Value Min 0.05 Max 30 0.2 Unit ms V Remarks
tR
VCC
0.2 V
4.5 V 0.2 V tOFF 0.2 V
Power supply drop time, power supply voltages and external reset input to retain RAM data in MB91220/S Satisfy the following reset input standard to retain the RAM data used in the single chip mode. Vcc (V) Voltage drop time External reset input standard (INITX) dropped 4.0 V 3.5 V Min 256 tcp Min 256 tcp
Vcc
4V 3.5 V 3.5 V
4V
INITX
256 tcp
To retain RAM data, enter 256 tcp of INITX or more before dropping VCC to 3.5 V or lower.
71
MB91220/S Series
(4) Clock Output Timing (VCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V) Parameter Cycle time SYSCLKSYSCLK SYSCLKSYSCLK Symbol tCYC tCHCL tCLCH Pin name SYSCLK SYSCLK SYSCLK Condition Value Min tCPT Max Unit ns ns ns Remarks *1 *2 *3
tCYC / 2 - 10 tCYC / 2 + 10 tCYC / 2 - 10 tCYC / 2 + 10
tCYC
tCHCL
tCLCH
VOH
VOH VOL
SYSCLK
*1 : tCYC is the frequency of one clock cycle including the gear cycle. *2 : The rating is under the conditions of "gear cycle x 1". When the gear cycle is set to 1/2, 1/4 or 1/8, use the formula below by entering 1/2, 1/4 or 1/8 in "n" respectively. ( 1 / 2 x 1 / n ) x tCYC - 10 *3 : The rating is under the conditions of "gear cycle x 1".
72
MB91220/S Series
(5) Normal Bus Access : Read/Write Operation (VCC = 4.0 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Parameter Symbol tCSLCH CS0X to CS3X setup tCSDLCH CS0X to CS3X hold tCHCSH tASCH Address setup tASWL tASRL tCHAX Address hold tWHAX tRHAX Valid address valid data input time WR0X, WR1X delay time WR0X, WR1X delay time WR0X, WR1X minimum pulse width Write data hold time RDX delay time RDX delay time RDX valid data input time Data setup RDX time RDX data hold time RDX minimum pulse width ASX setup ASX hold tAVDV tCHWL tCHWH tWLWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tCHASH RDX SYSCLK ASX RDX D00 to D15 SYSCLK A00 to A15 WR0X, WR1X A00 to A15 RDX A00 to A15 SYSCLK A00 to A15 WR0X, WR1X A00 to A15 RDX A00 to A15 A00 to A15 D00 to D15 SYSCLK WR0, WR1 WR0X, WR1X WR0X, WR1X, D00 to D15 SYSCLK RDX SYSCLK CS0X to CS3X Pin name Condition AWRxL : W02 = 0 AWRxL : W02 = 0 Value Min 3 -10 3 3 3 3 3 3 3 tCYC - 10 3 3 3 tCYC - 10 3 3 Max tCYC / 2 + 30 tCYC / 2 + 30 3 / 2 x tCYC + 45 10 10 10 10 tCYC - 30 tCYC / 2 + 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *1, *2 Remarks
*1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC x the number of expanded cycles) to the rated value. *2 : The rating is under the conditions of "gear cycle x 1". When the gear cycle is set to 1/2 to 1/16, use the formula below by entering 1/2 to 1/16 in "n" respectively. 73
MB91220/S Series
Formula : 3/ (2n) x tCYC + 45
tCYC VOH VOH VOH VOH
SYSCLK
tASLCH
tCHASH VOH
ASX
VOL tCSLCH tCSDLCH
tCHCSH VOH
CS0X to CS3X
VOL
tASCH
tCHAX VOH VOL
A00 to A15
VOH VOL
tCHRL tRLRH
tCHRH
RDX
tASRL
VOL tRHAX tRLDV tAVDV VOH VOH VOL tDSRH tRHDX
D00 to D15
VOL
tCHWL tWLWH VOL tASWL
tCHWH VOH tWHAX tWHDX
WR0X, WR1X
D00 to D15
VOH VOL
VOH VOL
74
MB91220/S Series
(6) Ready Input Timing (VCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V) Parameter RDY setup time SYSCLK SYSCLK RDY hold time Symbol tRDYS tRDYH Pin name SYSCLK RDY SYSCLK RDY Condition Value Min 15 0 ns Max Unit ns
tcyc
VoH
VoH VoL
SYSCLK
VoL
tRDYS
tRDYH
tRDYS
tRDYH
With RDY wait
VoH VoL VoL
VoH
Without RDY wait
VoH VoL
VoH VoL
75
MB91220/S Series
(7) UART Timing (TA : - 40 C to + 105 C; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Serial clock Cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Symbol tSCYC Pin name SCK0, SCK3 to SCK5 SCK0, SCK3 to SCK5, SOT0, SOT3 to SOT5 SCK0, SCK3 to SCK5, SIN0, SIN3 to SIN5 SCK0, SCK3 to SCK5 SCK0, SCK3 to SCK5, SOT0, SOT3 to SOT5 SCK0, SCK3 to SCK5, SIN0, SIN3 to SIN5 Condition Value Min 8 tCP Max Unit ns Remarks
tSLOV
- 80 100 60 4 tCP 4 tCP
+ 80
ns
In internal shift clock mode, output pin; CL = 80 pF+1 TTL
tIVSH tSHIX tSHSL tSLSH

ns ns ns ns In internal shift clock mode, output pin; CL = 80 pF+1 TTL
tSLOV
150
ns
tIVSH tSHIX
60 60

ns ns
Notes : * The above ratings are the values for clock synchronous mode. * CL is a load capacitance connected to pins during testing.
76
MB91220/S Series
* Internal Shift Clock Mode
tSCYC
SCK
0.8 V tSLOV
2.4 V 0.8 V
SOT
2.4 V 0.8 V tIVSH 0.8 Vcc tSHIX 0.8 Vcc 0.5 Vcc
SIN
0.5 Vcc
* External Shift clock Mode
tSLSH
tSHSL 0.8 Vcc 0.8 Vcc
SCK
0.5 Vcc tSLOV 2.4 V 0.8 V tIVSH 0.8 Vcc 0.5 Vcc
SOT
tSHIX 0.8 Vcc 0.5 Vcc
SIN
0.5 Vcc
77
MB91220/S Series
(8) Timer Input Timing (TA : - 40 C to + 105 C; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0 to TIN2, PWC0 IN0 to IN3 Condition Value Min 4 tCP Max Unit ns
* Timer Input Timing
tTIWH tTIWL
TINx INx
0.8 Vcc
0.8 Vcc 0.5 Vcc 0.5 Vcc
(9) Trigger input Timing (TA : - 40 C to + 105 C; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tTRGH, tTRGL Pin name INT0 to INT7, ATGX, RX0, RX1 Condition Value Min 5 tCP 1 Max Unit ns s At STOP mode Remarks
* Timer input timing
tTRGH tTRGL
INT0 to INT7 ATGX RX0,RX1
0.8 Vcc
0.8 Vcc 0.5 Vcc 0.5 Vcc
78
MB91220/S Series
6. A/D Converter Electrical Characteristics
(1) Electrical Characteristics (TA : - 40 C to + 105 C; VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Resolution Total error Non-linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Sampling time Compare time A/D conversion time Analog port input current Analog input voltage Standard voltage Power supply current Standard voltage supply current Variation between channels Symbol VOT VFST tSMP tCMP tCNV IAIN VAIN AVR + IA IAH IR IRH Pin name AN0 to AN23 AN0 to AN23 AN0 to AN23 AN0 to AN23 AVRH AVCC AVRH AVRH AN0 to AN23 Value Min AVSS - 1.5 LSB AVRH - 3.5 LSB 600 1200 990 1980 3 0 4.0 Typ AVSS + 0.5 LSB AVRH - 1.5 LSB 2.4 500 Max 10 3.0 2.5 1.9 AVSS + 2.5 LSB AVRH + 0.5 LSB 10 AVRH AVcc 4.7 5 900 5 5 Unit bit LSB LSB LSB V V ns ns ns ns s A V V mA A A A LSB *3 VAVRH = 5.0 V *3 Remarks
1 LSB = (AVRH - AVSS) / 1024 AVCC 4.5 V*1
4.0 V AVCC < 4.5 V*2
AVCC 4.5 V*1
4.0 V AVCC < 4.5 V*2
tSMP + tCMP AVCC VAIN AVSS
*1 : Assume that the output impedance of the external analog signal is 2.74 k or less. If the output impedance is high, the sampling time is longer than the standard value (refer to note) . For actual use, set tCNV tSMP + tCMP. *2 : Assume that the output impedance of the external analog signal is 0.7 k or less. If the output impedance is high, the sampling time is longer than the standard value (refer to note) . For actual use, set tCNV tSMP + tCMP. *3 : This defines the power supply current when the A/D converter is not in operation and the CPU is stopped (at VCC = AVCC = AVRH = 5.0 V) . (Continued)
79
MB91220/S Series
(Continued) Note : The external impedance of the analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient. Therefore, it adversely affects A/D conversion precision . * Analog input circuit model
R
Analog input
C
Comparator During sampling : ON
Note : The values are reference values.
R C 3.95 k (max) 17 pF (max)
80
MB91220/S Series
To satisfy the A/D conversion precision standard, adjust the register value and operating frequency, or decrease the external impedance in accordance with the relationship between the external impedance and minimum sampling time, in order to make the sampling time longer than the minimum value. * The relationship between the external impedance and minimum sampling time * At 4.5 V AVCC 5.5 V [External impedance = 0 k to 100 k]
100
[External impedance = 0 k to 20 k]
20
External impedance (k)
External impedance (k)
90 80 70 60 50 40 30 20 10 0 0 5 10 15
18 16 14 12 10 8 6 4 2 0 0 1 2 3
Minimum sampling time (s) * At 4.0 V AVCC < 4.5 V [External impedance = 0 k to 100 k]
100 90
Minimum sampling time (s)
[External impedance = 0 k to 20 k]
20 18
External impedance (k)
External impedance (k)
80 70 60 50 40 30 20 10 0 0 5 10 15
16 14 12 10 8 6 4 2 0 0 1 2 3 4
Minimum sampling time (s)
Minimum sampling time (s)
* If the sampling time is not sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Measure against noise for reference power supply (AVRH pin) It is recommended that a bypass capacitor of several F be input to the reference power supply (AVRH) . * About errors |AVRH - AVSS| becomes smaller, values of relative errors grow larger. * Others When placing a DC blocking capacitor between the external circuit and input pin,set the capacitance value by multiplying CSH and several thousands as a guideline in order to minimize the impact from dividing voltage capacitance with CSH. 81
MB91220/S Series
* Analog Input Equivalent Circuit Circuit in microcontroller Input pin AN0
rs
RSH
CSH
Comparator Input pin AN7 Analog channel selector
Vs
S/H circuit
External circuit
rS = 5 k or less RSH = approx. 2.5 k CSH = approx. 10 pF Note : These element parameters should be regarded as tentative values used only for design purposes. They do not guarantee the operation.
82
MB91220/S Series
(2) Term Definitions * Resolution Level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, the analog voltage can be resolved into 210 = 1024. * Total error Difference between actual and theoretical values, which is a total value derived from an offset error, gain error, non-linearity error and noise. * Linearity error Deviation between the value along a straight line connecting the zero transition point ("00 0000 0000""00 0000 0001") of a device and the full-scale transition point ("11 1111 1110""11 1111 1111") compared with the actual conversion values obtained. * Differential linearity error Deviation of input voltage, which is required for changing output code by1 LSB, from an ideal value.
Total error
3FFH 3FEH 3FDH Digital output {1 LSB x (N - 1) + 0.5 LSB} Actual conversion characteristics 0.5 LSB
004H 003H 002H 001H 0.5 LSB AVSS
(AVRL)
VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics
AVCC
(AVRH)
Analog input
Total error of digital output "N" = 1 LSB (Ideal value) =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVCC - AVSS [V] 1024
[LSB]
VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVCC - 1.5 LSB [V] VNT : A voltage at which digital output transits from (N - 1) H to NH. (Continued) 83
MB91220/S Series
(Continued) Non linearity error
3FFH 3FEH 3FDH Digital output Actual conversion characteristics {1 LSB x (N - 1) + VOT } (N + 1)H VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics
Differential linearity error
Ideal characteristics
Digital output
NH
004H 003H 002H
(N - 1)H
V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVCC Analog input
(AVRL)
Ideal characteristics 001H VOT (actual measurement value) AVSS
(AVRL)
(N - 2)H
AVCC Analog input
(AVRH)
AVSS
(AVRL)
Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N+1) T - VNT 1 LSB VFST - VOT 1022 -1 LSB [LSB] [V]
[LSB]
N : A/D converter digital output value VOT : Voltage at which digital output transits from "000H" to "001H." VFST : Voltage at which digital output transits from "3FEH" to "3FFH."
84
MB91220/S Series
7. Electrical Characteristics for the D/A Converter
Parameter Resolution Differential linearity error Symbol Conversion time Reference power supply current Analog output impedance IDVR IDVRS AVCC AVCC 2.0 2.00 162 3.0 920 0.1 3.9 s A A k (TA : - 40 C to + 105 C; VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Value Pin Unit Remarks Min Typ Max 0.45 8 3 bit LSB s At load capacitance 20 pF At load capacitance 100 pF TA = + 25 C At power down
85
MB91220/S Series
ORDERING INFORMATION
Part number MB91V220ACR-ES MB91F223PFV-GSE1 MB91F223SPFV-GSE1 Package 401-pin ceramic PGA (PGA-401C-A02) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) Remarks Evaluation product Sub clock support Sub clock not yet support
86
MB91220/S Series
PACKAGE DIMENSION
144-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 20.0 x 20.0 mm Gullwing Plastic mold 1.70 mm MAX 1.20g P-LFQFP144-20x20-0.50
(FPT-144P-M08)
Code (Reference)
144-pin plastic LQFP (FPT-144P-M08)
22.000.20(.866.008)SQ
* 20.000.10(.787.004)SQ
108 73
Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
109
72
0.08(.003)
Details of "A" part 1.50 -0.10
+0.20 +.008
.059 -.004
(Mounting height)
INDEX
0~8
0.100.10 (.004.004) (Stand off)
144
37
"A" LEAD No.
1 36
0.50(.020)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.220.05 (.009.002)
0.08(.003)
M
C
2003 FUJITSU LIMITED F144019S-c-4-6
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
87
MB91220/S Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
F0703

▲Up To Search▲

Price & Availability of MB91220

	To Download MB91220 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .